AMBA AHB · Module 19

Intermediate Interview Questions

The mechanism-level AHB interview questions that build on the fundamentals — wait states (the slave drives HREADY low to stretch the data phase while the master holds the address stable), bursts in depth (HBURST types, NONSEQ/SEQ beats, wrapping for cache-line fills), HTRANS (IDLE/BUSY/NONSEQ/SEQ), the pipeline effects (the slave captures address-phase control and uses it a cycle later), the two-cycle ERROR response (HREADY low then high so the pipelined master can cancel the next transfer), and HSIZE/alignment. Answer by tracing the mechanism through BOTH phases and connecting it to the pipeline. With model answers to the questions you'll actually be asked.

After the fundamentals, the interview moves to mechanisms — the questions that probe how AHB actually works once you're past "what is it." They group into six areas: wait states (the slave drives HREADY low to stretch the data phase while the master holds the address and control stable — how a fast bus serves slow slaves); bursts in depth (the HBURST types — SINGLE/INCR/WRAP4/INCR4/…; the first beat NONSEQ, the rest SEQ; wrapping bursts that wrap the address within an aligned region for cache-line fills); HTRANS (IDLE/BUSY/NONSEQ/SEQ — the transfer-type encoding); the pipeline effects (because the address phase is one cycle ahead, the slave must capture the address-phase control and use it a cycle later in the data phase); the two-cycle ERROR response (HREADY low then high so the pipelined master can cancel the already-issued next transfer); and HSIZE/alignment (the transfer size must be consistent with the address and burst). The way to answer well at this level is to trace the mechanism through BOTH phases — connect it back to the pipeline and explain the why. The single most valuable move is to trace the mechanism through the pipeline, because that shows you understand the pipeline, not just the signal names. This chapter gives model answers to the mechanism questions you'll actually be asked.

1. What Is It?

Intermediate AHB questions probe the mechanisms that build on the fundamentals; answering them well means tracing the mechanism through both phases and connecting it to the pipeline. The areas:

Wait states — the slave drives HREADY low to stretch the data phase; the master holds the address/control stable and waits. How a fast bus serves slow slaves.
Bursts in depth — HBURST types; first beat NONSEQ, rest SEQ; wrapping bursts wrap within an aligned region (cache-line fills).
HTRANS — IDLE (no transfer), BUSY (pause mid-burst), NONSEQ (start), SEQ (continue) — decoded in the address phase, acted on a cycle later.
Pipeline effects, two-cycle ERROR, HSIZE — the slave captures address-phase control for the data phase; ERROR is two cycles (low then high) so the master can cancel the next transfer; size must match the address/burst.

Figure 1 — the intermediate AHB interview topic map. Wait states: the slave drives HREADY low to stretch the data phase; the master holds the address and control stable while it waits; how a fast bus serves slow slaves. Bursts in depth: HBURST encodes the type (SINGLE/INCR/WRAP4/INCR4/…); the first beat is NONSEQ and the rest SEQ; wrapping bursts wrap within an aligned region for cache-line fills. HTRANS: IDLE (no transfer), BUSY (pause mid-burst), NONSEQ (start), SEQ (continue); decoded in the address phase, acted on a cycle later. Pipeline effects: the slave captures address-phase control and uses it a cycle later; an error interacts with the already-issued next address. HRESP two-cycle ERROR: cycle 1 ERROR + HREADY low, cycle 2 ERROR + HREADY high, so the pipelined master can cancel the next transfer. HSIZE + alignment: the size must match the address and burst. A strong intermediate answer connects the mechanism back to the pipeline.

So intermediate AHB questions are the mechanism check — interviewers use them to confirm you understand how the protocol works (not just what it is). The signal they're looking for is whether you can trace a mechanism through the pipeline — anyone can say "a wait state is when the slave isn't ready"; a candidate who understands says "the slave drives HREADY low, which stretches the data phase of the current transfer; the master holds the address and control constant — because the pipeline means the next address is already being presented — and waits until HREADY goes high." The trace-through-both-phases is the differentiator: it shows you understand the pipelined nature, the capture discipline, and the master-slave interaction — not just the signal. And the meta-signal is the same as the beginner round, deepened: connect the mechanism back to the pipeline — wait states stretch it, bursts use it, the two-cycle ERROR exists because of it. So intermediate AHB questions are the mechanisms, answered by tracing through both phases. So they're the depth that builds on the fundamentals.

Intermediate AHB questions = the mechanisms (wait states, bursts in depth, HTRANS, pipeline effects, two-cycle ERROR, HSIZE). Answer by TRACING the mechanism through BOTH phases and connecting it to the pipeline. The deepened meta-signal: wait states stretch the pipeline, bursts use it, ERROR is two cycles because of it

Intermediate AHB questions in one frame: the mechanisms that build on the fundamentals — answered well by tracing the mechanism through both phases and connecting it to the pipeline. The topics: wait states (the slave drives HREADY low to insert wait states, stretching the data phase; the master holds the address and control stable and waits — zero wait states means HREADY stays high); bursts in depth (HBURST encodes the type — SINGLE, INCR (undefined-length increment), INCR4/INCR8/INCR16 (fixed-length increment), WRAP4/WRAP8/WRAP16 (wrapping); the first beat is NONSEQ, the rest SEQ; wrapping bursts wrap the address within an aligned region — used for cache-line fills where the critical word is fetched first); HTRANS (the transfer-type encoding — IDLE (no transfer this cycle), BUSY (the master needs a pause mid-burst but stays committed to the burst), NONSEQ (the first beat / a single), SEQ (a continuation beat of a burst)); the pipeline effects (because the address phase is one cycle ahead, the slave must capture the address-phase control — HADDR/HWRITE/HSIZE/HTRANS/HBURST — and use it a cycle later in the data phase; an error or a cancelled transfer interacts with the already-issued next address); the two-cycle ERROR (ERROR is signaled over two cycles — cycle 1: HRESP=ERROR, HREADY=0; cycle 2: HRESP=ERROR, HREADY=1 — the two cycles exist because the bus is pipelined: by the time the error is signaled, the master has already issued the next transfer's address phase, and the two-cycle sequence gives the master a cycle to see it coming and cancel that next transfer cleanly); and HSIZE/alignment (the transfer size must be consistent with the address and the burst — a word burst uses word-aligned addresses; misalignment is a protocol bug). The answer approach — (1) state the mechanism (the fact); (2) trace it through both phases (address phase: what's presented; data phase: what happens a cycle later); (3) connect it to the pipeline and explain the why. The meta-signal: the pipeline underlies all of these — wait states stretch the pipeline, bursts use it, the two-cycle ERROR exists because of it. The common traps to avoid: forgetting the master holds the address stable during a wait, thinking a burst is repeated singles, and missing why ERROR is two cycles (the pipeline).

2. Why Does It Exist?

The intermediate round exists because, after the baseline, interviewers must probe how AHB works (the mechanisms) to distinguish a candidate who grasps the protocol's operation from one who only knows the terms — and the test is whether you can trace a mechanism through both phases and connect it to the pipeline, because that's what demonstrates real working knowledge.

The probe the mechanisms is the root: knowing what HREADY is (beginner) is different from knowing how a wait state works (the slave stretches the data phase, the master holds the address, the pipeline keeps the next address presented). So the intermediate round probes the mechanisms — how the protocol operates. So it exists to test working knowledge. So mechanisms come after fundamentals. So depth follows baseline.

The trace through both phases is the test: AHB is pipelined, so every mechanism spans the address phase and the data phase. A candidate who understands can trace a mechanism through both — what's presented in the address phase, what happens a cycle later in the data phase. So the intermediate round tests the trace — can you follow the mechanism through the pipeline? So it exists to test the two-phase trace. So tracing is the skill. So follow both phases.

The the pipeline is still the foundation is the deepened meta-signal: every intermediate mechanism connects to the pipeline — wait states stretch it, bursts use it, the two-cycle ERROR exists because of it. So connecting the mechanism to the pipeline signals you understand the foundation at the mechanism level. So the intermediate round deepens the pipeline signal. So the pipeline carries forward. So connect to the pipeline. So the intermediate round exists because: interviewers must probe the mechanisms (how AHB works — beyond the terms — the root); the test is tracing a mechanism through both phases (following it through the pipeline — the skill); and the pipeline is still the foundation every mechanism connects to (the deepened meta-signal). So intermediate AHB questions are the mechanism check — passed by tracing the mechanism through both phases and connecting it to the pipeline — demonstrating you understand how AHB works. So this chapter prepares you for the mechanisms. So trace through both phases, and connect to the pipeline.

3. Mental Model

Model answering an intermediate question as a mechanic being asked "how does the clutch work?" — not "what's a clutch." A parts-counter clerk says: "it's the pedal that lets you change gears." A mechanic who understands traces it: "you press the pedal, which moves the release bearing, which pushes the pressure plate's fingers, which lifts the clamp off the friction disc — so the engine spins free of the gearbox while you change gear (the input side) — then you release the pedal and the spring re-clamps the disc, re-coupling engine to gearbox (the output side). It works in two coordinated stages — disengage, then re-engage — and the timing between them is what makes a smooth shift." The interviewer instantly knows which one understands the mechanism vs knows the name. Tracing it through both stages is the tell.

A garage where a candidate is asked "how does the clutch work?" — not "what's a clutch" (a beginner question) but how it operates (an intermediate one). A parts-counter clerk who knows the name gives the bare function: "it's the pedal that lets you change gears" ("a wait state is when the slave isn't ready"). It's correct but shallow — it names the part, doesn't trace the mechanism. A mechanic who understands traces it through both stages: press the pedal → release bearing → pressure plate fingers → lifts the clamp off the disc → engine spins free (the input/disengage stage — the slave drives HREADY low → the data phase stretches → the current transfer holds); release the pedal → spring re-clamps → re-couples engine to gearbox (the output/re-engage stage — HREADY goes high → the data completes → the bus advances); and the timing between them is what makes the shift smooth (the master holds the address stable through the wait because the pipeline keeps the next address presented). The interviewer instantly knows: the clerk knows the name; the mechanic understands the mechanism. Tracing it through both stages — and explaining the coordination (the timing) — is the tell. And the meta-signal: a mechanic who keeps relating every mechanism back to the fundamental (engine-to-gearbox coupling) signals system understanding — like a candidate who connects every mechanism back to the pipeline.

This captures intermediate-question answering: "how does the clutch work?" = an intermediate (mechanism) AHB question; the clerk naming the part = a shallow, name-only answer; the mechanic tracing both stages = tracing the mechanism through both phases; the disengage stage = the address phase / the wait beginning; the re-engage stage = the data phase / the wait ending; the timing/coordination = the master-slave interaction across the pipeline; the interviewer knowing who understands = distinguishing mechanism-understanding from name-knowledge; relating every mechanism to the coupling = connecting every mechanism to the pipeline. Trace the mechanism through both phases, explain the coordination, connect it to the pipeline — and the interviewer knows you understand how AHB works.

Take a wait state and trace it through both phases, the way a strong answer would:

A wait state traced through both phases (slave holds HREADY low; master holds the address)

4 cycles

Figure 2 — two intermediate mechanisms traced. Top: a wait state — a single read where the slave holds HREADY low for two cycles (two wait states) while the master holds the address A1 stable; the slave raises HREADY on the third cycle and returns D1. The data phase stretches until HREADY is high, and the master holds the address constant throughout. Bottom: an INCR4 four-beat incrementing word burst from 0x10 — beat 1 NONSEQ at 0x10 starts the burst, then SEQ beats at 0x14, 0x18, 0x1C each step up by 4 (the word size). One address phase establishes the burst and the addresses follow the increment pattern — one logical transfer, not four singles.

The model's lesson: trace the mechanism through both phases, explain the coordination, and connect it to the pipeline. In the figure, the wait state isn't just "HREADY low" — it's the slave stretching the data phase while the master holds the address stable (the coordination), made necessary by the pipeline (the next address is already being presented). That's the mechanism, traced.

4. Real Hardware Perspective

The substance behind a strong intermediate answer is the mechanism detail from Modules 2–4 — so each question maps to a chapter, and the answer traces that mechanism through both phases.

The wait states: trace it — address phase: the master presents HADDR/control; data phase: the slave drives HREADY low to insert wait states, stretching the data phase; the master holds the address and control stable and waits; when the slave is ready, HREADY goes high and the data completes. So the answer traces the wait state through both phases and the master-slave coordination (see Slave Wait States, Master Behavior During Wait). So it's the pacing mechanism. So trace the hold.

Figure 3 — the two mechanisms behind the answers. Top, a wait state: a single read where the slave holds HREADY low for two cycles (two wait states) while the master holds the address stable; the slave raises HREADY on the third cycle and returns the data — the data phase stretches until HREADY is high. Bottom, an INCR4 four-beat incrementing word burst from 0x10: the first beat is NONSEQ at 0x10, then three SEQ beats at 0x14, 0x18, 0x1C, each stepping up by 4 because the size is a word — one address phase establishes the burst and the subsequent addresses follow the increment pattern (one logical transfer, not four singles).

The bursts and HTRANS: trace a burst — first beat: HTRANS=NONSEQ, the master presents the start address and the HBURST type/length; subsequent beats: HTRANS=SEQ, the address follows the pattern (increment by the size, or wrap within the aligned region); BUSY lets the master pause mid-burst while staying committed. So the answer traces the burst through its beats and the HTRANS encoding (see HBURST, HTRANS, INCR Bursts, WRAP4 / INCR4, BUSY Transfer). So it's the structured transfer. So trace the beats.

The the two-cycle ERROR and HSIZE: trace the ERROR — cycle 1: the slave drives HRESP=ERROR with HREADY low (a warning — and because the bus is pipelined, the master has already issued the next address); cycle 2: HRESP=ERROR with HREADY high (completing the errored transfer), giving the master a cycle to cancel the next transfer; HSIZE must match the address/burst alignment. So the answer traces the two-cycle response and connects it to the pipeline (see HSIZE and ERROR Response). So in practice, each intermediate answer traces the mechanism through both phases and connects it to the pipeline — the substance behind the trace. So in practice, know the mechanisms (Modules 2–4) and trace them. So that's the preparation.

5. System Architecture Perspective

At the interview level, the intermediate round is where the depth lives — passing it (tracing mechanisms through the pipeline) is what signals you can work with AHB (not just describe it), and it sets up the advanced round (arbitration, the interconnect, deadlock), which composes these mechanisms into system-level behavior.

The where the depth lives: the intermediate round is where the interviewer learns whether you can actually work with AHB — debug a wait-state issue, understand a burst on a waveform, reason about an error. A strong showing signals working competence; a weak showing caps the assessment at "knows the terms." So at the interview level, the intermediate round is where the depth lives. So pass it. So mechanisms signal competence.

The it sets up the advanced round: the advanced round (arbitration, the interconnect, deadlock) composes the intermediate mechanisms — arbitration manages who drives transfers (built of address/data phases and HREADY); deadlock involves the two-cycle error and wait interactions. So passing the intermediate round (the mechanisms) sets up the advanced round (the composition). So at the interview level, the mechanisms are the building blocks of the advanced discussion. So it sets up the depth. So master the mechanisms first. So at the interview level, the intermediate round is where the depth lives (passing it — tracing mechanisms — signals working competence) and sets up the advanced round (which composes these mechanisms into system-level behavior). So the intermediate round is where you prove you can work with AHB — making tracing mechanisms through the pipeline the key to signaling competence and unlocking the advanced discussion. So trace the mechanisms, prove competence, and earn the system-level questions. So the intermediate round is the depth.

6. Engineering Tradeoffs

Answering intermediate questions embodies the trace-through-both-phases, connect-to-the-pipeline, mechanism-over-name approach.

Trace through both phases vs name the signal. Tracing (address phase → data phase, the coordination) signals understanding; naming the signal is shallow. Trace it — the coordination across phases is the differentiator.
Connect to the pipeline vs isolated fact. Connecting the mechanism to the pipeline (waits stretch it, bursts use it, ERROR is two cycles because of it) signals foundation; an isolated fact misses it. Connect it.
The why vs the what. Why the mechanism works that way (e.g. why ERROR is two cycles) signals depth; the what alone is intermediate-shallow. Give the why.
Concrete trace vs vague gesture. A concrete trace (specific addresses, HTRANS values, cycle-by-cycle) is strong; a vague gesture is weak. Be concrete — walk the cycles.

The throughline: intermediate AHB questions probe the mechanisms — answer them by tracing the mechanism through both phases (address phase: what's presented; data phase: what happens a cycle later) and connecting it to the pipeline. The topics: wait states (slave drives HREADY low, stretches the data phase, master holds the address), bursts in depth (HBURST types, NONSEQ/SEQ, wrapping), HTRANS (IDLE/BUSY/NONSEQ/SEQ), the pipeline effects (capture address-phase control for the data phase), the two-cycle ERROR (low then high — because of the pipeline), and HSIZE/alignment. The meta-signal: the pipeline underlies all of these — connect each mechanism back to it. The common traps: forgetting the master holds the address during a wait, thinking a burst is repeated singles, missing why ERROR is two cycles. The intermediate round is where the depth lives — passing it (tracing mechanisms) signals you can work with AHB and sets up the advanced round.

The traps that weaken the intermediate round: forgetting the master HOLDS the address stable during a wait state (it doesn't change), thinking a burst is repeated singles (it's one address phase + a pattern), missing WHY ERROR is two cycles (the pipeline — to cancel the next transfer), and naming the signal without tracing the mechanism through both phases. Always connect the mechanism to the pipeline

A few mechanism-level traps weaken the intermediate round — get these wrong and the interviewer doubts you can work with AHB: (1) Forgetting the master holds the address stable during a wait. During a wait state (HREADY low), the master holds HADDR and all the control signals constant — it does not change the address or issue a new transfer. Saying the master "moves on" or "issues the next transfer" during a wait is wrong: the current transfer is still in its data phase (stretched), so the address phase can't advance. The pipeline is stalled, address held, until HREADY goes high. (2) Thinking a burst is repeated singles. (Carried from the beginner round, and more likely to be probed here.) A burst is one address phase (NONSEQ first beat) + several SEQ beats with a defined pattern — not independent singles. The interviewer may ask you to trace the addresses (0x10, 0x14, 0x18, 0x1C for an INCR4 word burst) or explain wrapping — get the pattern right. (3) Missing why ERROR is two cycles. The most-probed intermediate subtlety: ERROR is a two-cycle response (HREADY low then high) because the bus is pipelined — by the time the error is signaled, the master has already issued the next transfer's address phase, and the two-cycle sequence gives the master a cycle to see the error coming and cancel that next transfer cleanly. Knowing that ERROR is two cycles is intermediate; knowing why (the pipeline) is strong. Always give the why. (4) Naming the signal without tracing the mechanism. The general failure: answering an intermediate question at a beginner depth — naming HREADY or HBURST without tracing what happens across the two phases. Trace it — address phase, then data phase, then the coordination. (5) Forgetting alignment. HSIZE must be consistent with the address and burst — a word burst uses word-aligned addresses. Forgetting this misses a class of protocol bugs. The discipline: the master holds the address during waits, bursts are structured (one address phase + pattern), ERROR is two cycles because of the pipeline, trace the mechanism through both phases, and respect alignment. These are the mechanisms that signal working competence — trace them and you pass; name them shallowly and the interviewer caps you at "knows the terms." (See Slave Wait States, Master Behavior During Wait, and ERROR Response.)

7. Industry Example

A typical intermediate round — the mechanism questions and strong, traced answers.

After the fundamentals, the interviewer probes how the protocol works.

"Walk me through a wait state." Strong (traced): "In the address phase, the master presents the address and control. In the data phase, the slave drives HREADY low — it's not ready, so it inserts wait states, stretching the data phase. The master holds the address and all control signals stable and waits — it can't advance the pipeline because the current transfer is still in its data phase. When the slave is ready, it drives HREADY high, the data completes — for a read, HRDATA is valid that cycle — and the bus advances. So a slow slave can take as many cycles as it needs, and the master just waits." (Traced through both phases, with the hold.)
"Describe a four-beat incrementing burst." Strong: "It's an INCR4. The first beat has HTRANS=NONSEQ at the start address — say 0x10 — with HBURST=INCR4 and HSIZE=word. The next three beats have HTRANS=SEQ, with addresses 0x14, 0x18, 0x1C — each stepping up by 4, the word size. One address phase establishes the burst; the rest follow the increment pattern. It's one logical transfer, often a cache-line fill or DMA block, not four separate singles."
"What's the difference between INCR and WRAP?" Strong: "Both step the address by the size each beat, but WRAP wraps within an aligned region the size of the burst. A WRAP4 word burst starting at 0x14 goes 0x14, 0x18, 0x1C, then wraps to 0x10 — staying within the aligned 16-byte region. This is for cache-line fills where you fetch the critical word first and wrap around to fill the rest of the line."
"Why is the ERROR response two cycles?" Strong (the key why): "Because the bus is pipelined. The slave signals ERROR over two cycles — first HRESP=ERROR with HREADY low, then HRESP=ERROR with HREADY high. By the time the slave signals the error, the master has already issued the next transfer's address phase — that's the pipeline. The two-cycle sequence gives the master a cycle to see the error coming and cancel that next transfer cleanly, instead of it completing erroneously."
"What does HTRANS BUSY mean?" Strong: "BUSY lets the master pause mid-burst — it's committed to the burst but isn't ready with the next beat yet, maybe it's waiting on internal data. The address reflects the next beat, but BUSY tells the slave not to treat this as a real transfer — to wait for the master to resume with SEQ. It keeps the burst alive without forcing the master to produce a beat every cycle."
The meta-signal. Across the answers, you traced each mechanism through both phases and connected it to the pipeline — especially the two-cycle ERROR. The interviewer sees you can work with AHB and moves on to the advanced round.

The example shows the intermediate round and strong, traced answers: each traced through both phases, connected to the pipeline, avoiding the traps (the master holds the address, bursts are structured, ERROR is two cycles because of the pipeline). This signals working competence and earns the advanced round. This is how you show you can work with AHB.

8. Common Mistakes

Intermediate-question misconceptions

"During a wait, the master issues the next transfer." No — the master holds the address and control stable. The current transfer is still in its data phase; the pipeline is stalled until HREADY is high.
"A burst is several singles." No — one address phase (NONSEQ) + several SEQ beats with a defined pattern. Trace the addresses.
"ERROR is two cycles just because the spec says so." No — it's two cycles because the bus is pipelined: to give the master a cycle to cancel the already-issued next transfer.
"WRAP and INCR are the same." No — WRAP wraps within an aligned region (cache-line fills); INCR keeps incrementing.
"BUSY ends the burst." No — BUSY pauses the burst (the master stays committed); it resumes with SEQ. IDLE is the no-transfer state.
"Naming the signal is enough." No — trace the mechanism through both phases. Naming is beginner-depth; tracing is intermediate-depth.

9. Interview Insight

The intermediate round is where the depth lives — tracing the mechanism through both phases, connecting it to the pipeline, and getting the subtleties (the hold, the pattern, the two-cycle why) right are the signals.

Figure 4 — a strong intermediate round in one card: topics (wait states, bursts in depth, HTRANS, pipeline effects, two-cycle ERROR, HSIZE/alignment); answer by tracing the mechanism through BOTH phases and connecting it to the pipeline; the key insight — a wait stretches the data phase, the master holds the address stable, ERROR is two cycles because the bus is pipelined; traps — address not held during waits, burst ≠ repeated singles, forgetting why ERROR is two cycles. The senior point: trace the mechanism through the pipeline and explain the why.

The way to carry the intermediate round: trace each mechanism through both phases, connect it to the pipeline, and get the subtleties right. The interviewer is checking whether you can work with AHB — follow a mechanism through the pipelined operation, not just name the signals. The most valuable move is to trace concretely — specific addresses, HTRANS values, cycle-by-cycle — and connect it to the pipeline (the foundation that makes the mechanism necessary). Get the subtleties right (the master holds the address during waits, bursts have a defined pattern, ERROR is two cycles because of the pipeline), and you'll pass the depth round and earn the advanced (arbitration, interconnect, deadlock) questions.

10. Practice Challenge

Practice the intermediate round.

Trace a wait state. Walk a two-wait-state read cycle by cycle — what the slave drives, what the master holds.
Burst patterns. Trace INCR4 and WRAP4 word bursts from 0x14 — the addresses and HTRANS values.
The two-cycle why. Explain why ERROR is two cycles (the pipeline — to cancel the next transfer).
HTRANS. Distinguish BUSY from IDLE — commitment to a burst vs no transfer.
The write pipeline. Explain when the slave samples HWDATA relative to the address — and why it must register the address.

11. Key Takeaways

Intermediate AHB questions probe the mechanisms — wait states, bursts in depth, HTRANS, the pipeline effects, the two-cycle ERROR, HSIZE/alignment.
Answer by tracing the mechanism through both phases — address phase: what's presented; data phase: what happens a cycle later; then the coordination. Tracing is intermediate-depth; naming is beginner-depth.
Connect every mechanism to the pipeline — wait states stretch it, bursts use it, the two-cycle ERROR exists because of it. The pipeline is still the foundation.
Get the subtleties right — the master holds the address stable during a wait; a burst is one address phase + a pattern (not singles); ERROR is two cycles because of the pipeline; WRAP wraps within an aligned region; BUSY pauses a burst (≠ IDLE).
The intermediate round is where the depth lives — passing it (tracing mechanisms) signals you can work with AHB and sets up the advanced round.
Substance behind the trace — each answer draws on the mechanism detail from Modules 2–4. Know it and trace it concretely (specific addresses, HTRANS values, cycles).

12. What Comes Next

You can now trace the mechanisms. The next chapters cover the system-level and specialized rounds:

Advanced Interview Questions (next) — arbitration, the interconnect, deadlock (composing these mechanisms into system-level behavior).
Waveform Interpretation, Design Questions, Verification Questions, and the rest — reading timing, RTL prompts, and testbench strategy.

To revisit the mechanisms these questions cover, see Slave Wait States, Master Behavior During Wait, HBURST, HTRANS, WRAP4 / INCR4, and ERROR Response.