UVM tutorials & labs.
The complete UVM path — from “what is verification?” through the factory, config_db, phasing, sequences, agents, TLM, scoreboards, coverage, and RAL, to designing, scaling, and debugging industrial UVM environments. Assumes the SystemVerilog track as a prerequisite.
Tutorials
Learn UVM from beginner to advanced through structured tutorials.
Labs
Practice UVM using progressively challenging hands-on labs.
What UVM is
UVM — the Universal Verification Methodology — is a SystemVerilog class library and a set of conventions for building verification environments that can be reused across blocks, projects and companies. It supplies the pieces a testbench always needs: components with a defined construction and run order, a transaction-level messaging scheme, a factory for substituting types without editing the environment, a configuration database for passing settings down the hierarchy, and a register layer for modelling a device's programming interface. Standardised through Accellera and now IEEE 1800.2, it is the default methodology for functional verification of complex SoCs.
Why it exists
Before UVM, every team built its own testbench structure, and none of it moved between projects. The cost was not the writing — it was that a verification environment for one block taught you nothing about the next, and IP delivered with a testbench could not be integrated without rewriting it. UVM's value is that it fixes the shape of the environment so that agents, sequences and scoreboards become portable assets, and an engineer joining a project already knows where everything is.
The part engineers get wrong
The reuse comes from one separation: a sequence describes what a transaction means, and a driver decides how that meaning becomes pin wiggles. Keep the two apart and the same stimulus runs against a block, a subsystem and a chip-level model without change. Blur them — put protocol timing inside a sequence, or decisions inside a driver — and you have written a conventional directed testbench wearing UVM class names, with all of the ceremony and none of the portability.
Before you start
- SystemVerilog classes, inheritance and polymorphism
- Interfaces and virtual interfaces — the bridge from the class world to signals
- Constrained randomization basics: rand fields and constraint blocks
- A working idea of what a testbench must do: drive, observe, check
What you will be able to do
- Build an agent from driver, sequencer and monitor, and know when to make it passive
- Write sequences that describe stimulus intent without embedding pin timing
- Connect components with TLM ports and analysis exports
- Use the factory to override a type or a single instance without editing the environment
- Retrieve configuration reliably, and debug a config_db lookup that silently missed
- Build a scoreboard that compares expected against observed and reports usefully
- Reason about phase order and objections when a test ends too early or hangs
The learning path
- Why a methodology existsThe reuse problem UVM was created to solve
- Class hierarchyuvm_object vs uvm_component, and what each is for
- TransactionsSequence items — the unit of intent that flows through the environment
- Agent architectureDriver, sequencer, monitor, and active vs passive modes
- TLM connectionsPorts, exports and analysis broadcasting between components
- Configuration and factoryconfig_db scope rules and type/instance overrides
- Phases and objectionsConstruction, connection and run-phase lifetime control
- Scoreboards and coverageChecking correctness and measuring what was verified
- Register layerModelling the programming interface with UVM RAL
Core concepts
New to UVM? Work through the curriculum in order — each lesson assumes the one before it, and the sequence is what turns the roadmap above into working knowledge.
Already working with it? Use the core-concept links above to jump straight to the topic you need; each one opens the lesson that covers it in most depth.
Where this leads
Standards: Accellera / IEEE 1800.2 — The UVM standard — the normative definition of the base classes used throughout