WRAP8 & INCR8 Bursts

Chapter 8.4 covered the 4-beat bursts and the wrap mechanics. This chapter covers the 8-beat pair: INCR8 and WRAP8 — the same patterns scaled to 8 beats. INCR8 is eight linearly-incrementing beats; WRAP8 is eight beats wrapping within the aligned block of size 8 × beat-size (32 bytes for words). Mechanically, WRAP8 is just WRAP4 with a bigger block — twice the beats, twice the block. It serves 8-word cache line fills (a common line size), critical-word-first. Because the mechanics carry over directly, this chapter's distinct contribution is the burst-length choice: why a system picks 4, 8, or 16 beats — the tradeoff between throughput (longer bursts amortize more) and latency/fairness (longer bursts hold the bus longer), and how WRAP length is set by the cache line size.

1. What Is It?

INCR8 and WRAP8 are 8-beat fixed-length bursts — the 4-beat patterns (chapter 8.4) scaled to 8 beats:

• INCR8 — eight beats, address incrementing linearly (each beat = previous + beat size). Marches through eight consecutive locations.
• WRAP8 — eight beats, address incrementing but wrapping within the aligned block of size 8 × beat-size (32 bytes for words). The eight beats stay inside one aligned 32-byte block.

The mechanics are identical to WRAP4/INCR4, just scaled: the only change is the block size (and thus the wrap boundary), which is now 8 × beat-size instead of 4 × beat-size. WRAP8 wraps the lower address bits within the aligned 32-byte block (for words); INCR8 increments linearly. Both declare exactly 8 beats via HBURST, giving precise prefetch. So learning WRAP8/INCR8 is just applying the chapter-8.4 mechanics with a bigger block — the wrap-the-low-bits, stay-in-the-aligned-block, critical-word-first behavior all carry over. A WRAP8 from 0x08 (words) goes 0x08, 0x0C, 0x10, 0x14, 0x18, 0x1C, then wraps to 0x00, 0x04.

2. Why Does It Exist? (And why choose 8 beats?)

The 8-beat bursts exist for the same reasons as the 4-beat ones (known-size blocks with precise prefetch; WRAP8 for cache fills) but at a larger block size — and the deeper question this chapter addresses is why a system would choose 8 beats over 4 or 16.

The existence rationale mirrors chapter 8.4: INCR8 serves a known 8-beat linear block; WRAP8 serves an 8-word cache line fill (critical-word-first, wrapping within the aligned 32-byte line). The 8-beat length exists because 8-word cache lines are common — many CPUs use 32-byte (8-word) lines, which fill with WRAP8. So WRAP8 exists to serve that common line size, just as WRAP4 serves 4-word lines. The fixed 8-beat count gives precise 8-beat prefetch. So the 8-beat types are the 4-beat types' rationale at the 8-beat scale.

The burst-length choice is the new content: why 8 (versus 4 or 16)? It's a throughput-vs-latency tradeoff (chapter 8.1). Longer bursts (more beats) amortize the per-transfer overhead — address setup, arbitration — over more beats, and let memory stream more per row-open, giving higher throughput. But longer bursts also hold the bus/path longer, which can increase latency for other masters (they wait longer for the bus) and reduce fairness. So there's a tension: longer = more throughput but more bus-hold (worse latency for others); shorter = less throughput but more responsive.

So 8 beats is often the balanced choice: it amortizes overhead well (better than 4) while not holding the bus as long as 16 (better latency than 16). For caches, 8-word (32-byte) lines are a common sweet spot — enough to amortize the fill and exploit spatial locality, without the latency of a 16-word line. So a system chooses 8-beat bursts (WRAP8 for its 8-word cache lines) when it wants balanced throughput and latency. The choice isn't arbitrary: for WRAP, the length is determined by the cache line size (an architectural choice balancing miss rate, fill latency, and spatial locality); for INCR, the length is chosen (and often bounded) to balance amortization against fairness. The 8-beat types exist as this balanced middle option.

3. Mental Model

Model the burst-length choice as deciding how many items to carry per trip from the car to the kitchen — more items per trip means fewer trips (efficiency) but a heavier load and a longer time before you can do anything else (you're committed to the trip).

Unloading groceries (moving data), you choose how many bags to carry per trip (the burst length). Carrying few bags per trip (a 4-beat burst) means more trips (more overhead — more walks back and forth) but each trip is quick and you're free between trips (low latency — you can do other things). Carrying many bags per trip (a 16-beat burst) means fewer trips (less overhead, more efficient) but each trip is heavy and long, and you're committed for the whole trip (high bus-hold — you can't do anything else until you've carried all those bags in). Carrying a moderate number (an 8-beat burst) balances the two — reasonably few trips, but not so heavy that you're committed forever. And for a specific known load — like exactly one box that holds 8 items (a cache line) — you carry exactly that box (WRAP8 for an 8-word line): the load size is determined by what you're carrying.

This captures the choice: items per trip = burst length; fewer trips = less overhead (throughput); committed for the trip = bus-hold (latency for others); moderate load = the balanced 8-beat choice; a known box of 8 = WRAP8 sized to an 8-word cache line. More per trip is more efficient but commits you longer — the throughput-vs-latency tension.

Watch a WRAP8 wrap (8 beats):

The model's lesson: WRAP8 is WRAP4 with a bigger box — eight beats wrapping within the aligned 32-byte block, and the length is the load you chose (the cache line size). In the waveform, the address wraps from 0x1C back to 0x00 after the block's top, keeping all eight beats in the aligned 32-byte line. Same wrap mechanic, bigger block.

4. Real Hardware Perspective

In hardware, WRAP8/INCR8 are identical to WRAP4/INCR4 except the wrap boundary is 8 × beat-size instead of 4 × beat-size — the manager's address generator uses a bigger modular increment — and the burst-length choice manifests as the cache line size and the interconnect's burst-length limits.

The address generation scales directly: for WRAP8 of words, the block is 32 bytes (lower 5 bits index within it), so the manager increments the low 5 bits mod 32 (wrapping at 32), keeping the upper bits fixed — versus WRAP4's low-4-bits-mod-16. INCR8 is a plain increment for 8 beats. So the only hardware change from the 4-beat types is the number of low bits that wrap (5 vs 4) and the beat count (8 vs 4). The wrap mechanic — modular increment on the in-block bits — is identical. So a manager supporting WRAP4 and WRAP8 uses the same logic parameterized by the boundary (from HBURST/HSIZE). This parameterization is why the WRAP types scale cleanly: one wrap mechanism, different boundaries.

The cache line size is the hardware embodiment of the burst-length choice for WRAP. A CPU's cache line size (a design parameter) determines the WRAP burst used for fills: a 32-byte (8-word) line fills with WRAP8. So choosing the cache line size is choosing the WRAP burst length. Cache designers pick the line size to balance miss rate (larger lines exploit spatial locality, fewer misses), fill latency (larger lines take longer to fill), and the WRAP burst's bus-hold. 32-byte (8-word) lines are a common balance, hence WRAP8 is common. So the WRAP8 burst length reflects a cache-architecture decision baked into the hardware.

The interconnect's burst-length handling matters for longer bursts. An interconnect (chapter 12.x) may have limits on how long a burst can hold a path, for fairness — so it might require long bursts to be broken at certain boundaries, or it arbitrates between bursts. For INCR (especially long ones), this is where the system bounds the length (chapter 8.3). So the hardware that enforces the throughput-vs-latency balance is partly the interconnect: it bounds how long a master can hold the path, capping burst length for fairness. The 8-beat length is short enough to usually be fine, while 16-beat (chapter 8.6) pushes the bus-hold further.

A hardware note on prefetch scaling: with WRAP8/INCR8 declaring 8 beats, the memory controller prefetches the exact 8-beat sequence (for WRAP8, the exact wrapped order). The longer fixed burst lets the controller stream more from an opened row before needing to do anything else — better row-open amortization than a 4-beat burst. So longer fixed bursts give the memory more to stream per row-open, which is the throughput benefit of longer bursts at the memory level. This is concretely why longer bursts amortize better: more beats per row-open.

5. System Architecture Perspective

At the system level, the 8-beat bursts represent the balanced point in the burst-length spectrum, and the choice of burst length (cache line size for WRAP, bounded length for INCR) is a key architectural decision balancing throughput, latency, and fairness.

The throughput-vs-latency balance is a real architectural tension. A system that wants maximum memory throughput might favor longer bursts (16-beat) to amortize overhead most; a system that wants low latency and good multi-master responsiveness might favor shorter bursts (4-beat) to free the bus sooner. 8-beat sits in the middle — good amortization without excessive bus-hold. So an architect chooses the burst length (via cache line size, DMA burst configuration, interconnect limits) to fit the system's throughput/latency priorities. There's no universally-right length; it's a per-system balance, and 8 beats is a common compromise.

The cache line size decision (which sets the WRAP length) is one of the most consequential: it affects miss rate (spatial locality), miss latency (fill time), memory bandwidth (burst efficiency), and cache capacity utilization. Larger lines (16-word, WRAP16) exploit more spatial locality and amortize fills better but waste bandwidth/capacity on unused words and have longer fill latency; smaller lines (4-word, WRAP4) are the opposite. 8-word (32-byte) lines, filled by WRAP8, are a very common balance. So the WRAP8 burst length is tied to this central cache-design decision — the burst length is downstream of the cache line size, which balances multiple factors. An architect tuning cache performance is, in effect, choosing the WRAP burst length.

For INCR bursts, the length choice is about DMA/streaming configuration and fairness: a DMA engine's burst length (how many beats per burst before re-arbitrating) balances its throughput against other masters' access to the bus. Longer INCR bursts give the DMA more throughput but starve others longer; shorter ones are fairer but less efficient for the DMA. So systems configure DMA burst lengths (often 8 or 16 beats) and bound them via the interconnect to balance the DMA's needs against system fairness. So the INCR burst length is a tunable that balances a streaming master's throughput against multi-master fairness — another instance of the throughput-vs-latency tradeoff. The 8-beat length is a common DMA burst size for this balance.

So at the system level, the 8-beat bursts embody the balanced burst length, and the broader lesson is that burst length is a key architectural tunable — set by the cache line size for WRAP (balancing miss rate, latency, bandwidth) and by DMA/interconnect configuration for INCR (balancing throughput and fairness). 8 beats is a frequent sweet spot, which is why WRAP8/INCR8 are widely used.

6. Engineering Tradeoffs

The 8-beat bursts and the burst-length choice embody the throughput-vs-latency balance.

• 8 beats vs 4 beats. 8-beat bursts amortize overhead better and exploit more spatial locality (for cache lines) than 4-beat, at the cost of holding the bus longer (more latency for others). 8 is the balanced step up from 4.
• 8 beats vs 16 beats. 8-beat bursts hold the bus less long (better latency/fairness) than 16-beat, at the cost of amortizing overhead less and exploiting less spatial locality. 8 is the balanced step down from 16.
• WRAP length = cache line size. For WRAP, the length is determined by the cache line size, which itself balances miss rate, fill latency, bandwidth, and capacity. Choosing the line size chooses the WRAP length — a central, multi-factor cache-design decision.
• INCR length = throughput vs fairness. For INCR (DMA/streaming), longer bursts give the streaming master more throughput but starve others; the length is configured and bounded to balance throughput against multi-master fairness.

The throughline: WRAP8/INCR8 are the 4-beat patterns scaled to 8 beats — the balanced point in the burst-length spectrum. The wrap mechanics are identical (bigger block, boundary 8 × beat-size); the distinct lesson is the burst-length choice: longer bursts trade higher throughput (more amortization, more streaming per row-open) for longer bus-hold (worse latency/fairness for other masters). 8 beats is a common balanced compromise — set by 8-word cache lines for WRAP, and by DMA configuration for INCR.

7. Industry Example

Trace the 8-beat bursts and the length choice in a system with 8-word cache lines.

A CPU with 32-byte (8-word) cache lines, a DMA engine, and other masters share an AHB.

• A cache miss — WRAP8 fill. The CPU misses on a load to 0x08. Its 8-word cache line is the aligned 32-byte block 0x00–0x1F. The cache issues a WRAP8 burst from the critical word 0x08: 0x08, 0x0C, 0x10, 0x14, 0x18, 0x1C, then wraps to 0x00, 0x04 — fetching the whole aligned 8-word line, critical-word-first. The CPU resumes on 0x08 while the rest fills. The 32-byte line uses WRAP8 because the line size is 8 words.
• Why 8-word lines. The CPU's designers chose 8-word lines as a balance: large enough to exploit spatial locality (fewer misses) and amortize the fill, but not so large that fill latency and bus-hold (a 16-word WRAP16) hurt. So WRAP8 is the fill burst, reflecting that 8-word-line decision.
• A DMA copy — INCR8 chunks. The DMA engine copies a large buffer using INCR8 bursts (8-beat chunks), re-arbitrating between them. 8-beat chunks give the DMA good throughput (amortizing over 8 beats) while freeing the bus periodically so the CPU and other masters aren't starved. The DMA could use INCR16 for more throughput, but 8-beat balances its throughput against fairness.
• The fairness consideration. If the DMA used very long bursts (16-beat or unbounded INCR), the CPU's cache fills would wait longer for the bus, increasing the CPU's effective miss latency. By using 8-beat DMA bursts, the system keeps the bus responsive — the CPU's fills don't wait too long. So the 8-beat length balances the DMA's throughput against the CPU's latency. This is the throughput-vs-latency tradeoff in action.
• Contrast smaller/larger. A system with 16-byte (4-word) lines would use WRAP4 (lower latency, less spatial locality); one with 64-byte (16-word) lines would use WRAP16 (more locality, more bus-hold). The 32-byte/WRAP8 choice is the common middle. Similarly, DMA bursts of 4/8/16 beats trade throughput against fairness.

The example shows the 8-beat bursts as the balanced choice: WRAP8 for 8-word cache fills (a common line size balancing locality and latency), and INCR8 for DMA chunks (balancing the DMA's throughput against system fairness). The 8-beat length keeps the bus responsive for multiple masters while still amortizing overhead well — the sweet spot the burst-length tradeoff often lands on.

8. Common Mistakes

9. Interview Insight

WRAP8/INCR8 are usually tested together with the burst-length tradeoff — knowing the scaling and the throughput-vs-latency balance is the signal.

The answer that lands covers the scaling and the tradeoff: "INCR8 and WRAP8 are the 8-beat fixed-length bursts — the same patterns as INCR4/WRAP4, just scaled to 8 beats. INCR8 increments linearly through 8 consecutive locations; WRAP8 wraps within the aligned block of size 8 times the beat size — 32 bytes for words — so a WRAP8 from 0x08 goes 0x08 through 0x1C, then wraps to 0x00, 0x04. WRAP8 serves an 8-word cache line fill, critical-word-first, which is a common line size. The interesting part is the burst-length choice: longer bursts like 8 or 16 amortize the address and arbitration overhead over more beats and let memory stream more per row-open, giving higher throughput — but they hold the bus longer, increasing latency for other masters. So 8 beats is often a balanced choice: good amortization without too much bus-hold. For WRAP, the length is set by the cache line size; for INCR, it's configured and bounded to balance a streaming master's throughput against fairness." The scaling, the throughput-vs-latency tradeoff, and the cache-line-size/length connection are the senior signals.

10. Practice Challenge

Reason from the 8-beat bursts and the length tradeoff.

1. Scale the pattern. Give the WRAP8 and INCR8 address sequences for words starting at 0x08.
2. The boundary. State the WRAP8 block size for words and which address bits wrap.
3. Read the waveform. From Figure 3, identify where the WRAP8 wraps and confirm it stays in the block.
4. The tradeoff. Explain how burst length trades throughput against latency/fairness.
5. Choose a length. Explain what determines the WRAP length (cache fills) and the INCR length (DMA).

11. Key Takeaways

• INCR8 and WRAP8 are the 4-beat patterns scaled to 8 beats — INCR8 increments linearly; WRAP8 wraps within the aligned block of size 8 × beat-size (32 bytes for words).
• Same wrap mechanic, bigger block — WRAP8 wraps the lower address bits within the aligned 32-byte block; a WRAP8 from 0x08 (words) goes 0x08…0x1C, then 0x00, 0x04.
• WRAP8 serves 8-word cache line fills (a common line size), critical-word-first; INCR8 serves a known 8-beat linear block.
• Burst length is a throughput-vs-latency tradeoff — longer bursts amortize overhead more and stream more per row-open (higher throughput) but hold the bus longer (worse latency/fairness for other masters).
• For WRAP, the length = the cache line size (a cache-design choice balancing miss rate, latency, bandwidth); for INCR, the length is configured and bounded for DMA throughput vs fairness.
• 8 beats is a common balanced choice — good amortization without excessive bus-hold — but not universally optimal; 4 and 16 fit different priorities.

12. What Comes Next

You now understand the 8-beat bursts and the burst-length tradeoff. The next chapter covers the longest fixed bursts:

• 8.6 — WRAP16 & INCR16 Bursts (coming next) — the 16-beat fixed-length bursts (largest cache lines, longest blocks, maximum amortization).

To revisit the 4-beat bursts and wrap mechanics, see WRAP4 & INCR4 Bursts; for the undefined-length type, INCR (Undefined-Length) Bursts; for the overview, Burst Overview. For the HBURST signal, see HBURST. For the broader protocol map, see the AMBA family overview.