Test how you think, not just what you remember
Practice engineering reasoning across RTL, verification, protocols, and semiconductor systems with questions built around real concepts, failure modes, and design decisions.
Free practice available · Advanced packs optional
01Core HDL & RTL
Test RTL semantics, synthesisable design reasoning, concurrency, and hardware behaviour.
Verilog HDL
RTL modeling, timing, synthesis and debug reasoning, anchored in real Verilog design work.
SystemVerilog
Data types, OOP, randomization, constraints, assertions and functional coverage.
VHDL
Entities, architectures, strong typing, signals versus variables, and the concurrent execution model.
02Verification
Practise verification methodology, debugging, coverage, assertions, and failure analysis.
03Protocols & Interconnect
Reason about bus protocols the way an integrator does — phase timing, handshakes, error responses, and the RTL and checkers that enforce them.
AMBA APB
SETUP/ACCESS timing, wait states, PSLVERR, manager and subordinate RTL, assertions and waveform debugging.
AMBA AHB
Pipelined address and data phases, HTRANS sequencing, HREADY, bursts, error responses and waveform forensics.
AMBA AXI
Five independent channels, the VALID/READY contract, bursts and the 4 KB boundary, IDs, outstanding transactions and ordering.
In authoring
Protocols · STA · Scripting · C / C++