Boundary Wrapping

Chapter 8.7 gave the address formulas. This chapter zooms into the wrap boundary itself — the structural reason WRAP bursts exist. The boundary sits at the naturally-aligned block size: B = L × s (beat count × beat size), and a WRAP burst is confined to exactly one aligned B-byte block, wrapping at its boundaries. Two consequences follow. First, this alignment matches a cache line (which is also naturally aligned to its size) — the deep reason WRAP serves cache fills. Second, because WRAP stays within its aligned block, it can never cross into another address region — whereas an INCR burst could, which is why AHB has the guideline that bursts must not cross an address-decode boundary (commonly stated as not crossing a 1KB boundary). So the wrap boundary isn't just an address-math detail; it's what gives WRAP its confinement guarantee — matching cache lines and keeping the decode stable.

1. What Is It?

The wrap boundary is the address at which a WRAP burst wraps — and it sits at the naturally-aligned block of size B = L × s (beat count times beat size). The memory is conceptually divided into back-to-back aligned B-byte blocks, and a WRAP burst is confined to exactly one of them, wrapping at its boundaries.

The key word is aligned. The boundary isn't at an arbitrary address — it's at a multiple of B, so the block is naturally aligned to its own size. A WRAP4 of words (B=16) wraps at 16-byte-aligned boundaries; a WRAP8 (B=32) at 32-byte boundaries; a WRAP16 (B=64) at 64-byte boundaries. So the WRAP burst always lives within a naturally-aligned block of its size, never straddling two blocks. This confinement to an aligned block is the structural property that everything else about WRAP follows from — it's why WRAP matches cache lines (also aligned) and why WRAP never crosses an address region.

2. Why Does It Exist?

The aligned wrap boundary exists because the two things WRAP serves — cache lines and decode stability — both require confinement to a naturally-aligned block. The alignment isn't incidental; it's what makes WRAP useful.

The first reason is the cache line. A cache line is, by hardware necessity, naturally aligned to its size — a 16-byte line occupies an aligned 16-byte block, a 64-byte line an aligned 64-byte block. (This alignment is fundamental to how caches index and tag: the line's address bits split into tag, index, and offset, with the line aligned to its size.) So for a WRAP burst to fill exactly one cache line, it must be confined to exactly one naturally-aligned block of the line's size — which is precisely what the aligned wrap boundary provides. So WRAP's aligned boundary exists to match the cache line's alignment: B equals the line size, and the WRAP block equals the aligned line. The alignment is the link between WRAP and caches — a WRAP burst's confinement to an aligned block is a cache line's confinement to its aligned block. Without the alignment, WRAP couldn't cleanly fill a cache line.

The second reason is decode stability. The AHB address decoder selects a subordinate based on the address (chapter 3.9); different address regions map to different subordinates. If a burst's addresses crossed a decode boundary — moving from one subordinate's region into another's — the burst would change which subordinate it's talking to mid-burst, which is broken (a single burst must stay with one subordinate). A WRAP burst, confined to its aligned block, cannot cross such a boundary (as long as the decode regions are aligned, which they are) — so it stays with one subordinate by construction. So the aligned confinement also guarantees decode stability: a WRAP burst never wanders into another subordinate's region. This is the second reason the boundary is aligned — to keep the burst within one subordinate.

So INCR, which is not confined (it increments linearly and can cross boundaries), needs the explicit guideline: a burst must not cross an address-decode boundary, commonly stated as not crossing a 1KB address boundary (the AHB convention for the minimum decode-region granularity). So the manager must ensure an INCR burst stays within one subordinate's region (within a 1KB-aligned boundary), breaking longer transfers at boundaries if needed. WRAP needs no such guideline — its aligned confinement handles it automatically. So the boundary-crossing rule exists for INCR (which can cross), while WRAP's aligned boundary makes the rule automatic. Both the cache-line match and the decode stability are why WRAP's boundary is aligned — and why INCR needs the boundary rule that WRAP gets for free.

3. Mental Model

Model the aligned wrap boundary as a running track with numbered lanes grouped into aligned sections — a WRAP runner stays in their assigned section, looping back at the section's edge, while an INCR runner could run straight off into the next section.

A track is divided into aligned sections (the aligned B-byte blocks), each belonging to a different group (a different subordinate's region). A WRAP runner is assigned to one section and runs within it — when they reach the section's edge (the aligned boundary), they loop back to the section's start and continue, never leaving their section. So they always stay in their assigned group's section (their cache line, their subordinate). An INCR runner, by contrast, just runs straight ahead — when they reach their section's edge, they keep going into the next section (the next group's territory), which is a problem if they weren't supposed to leave. So the INCR runner needs a rule: "don't run past your section's boundary" (don't cross the 1KB decode boundary). The WRAP runner needs no such rule — looping within the section is built into how they run. The sections being aligned is what makes "one section = one group" clean.

This captures the boundary: aligned sections = naturally-aligned B-byte blocks (= cache lines = within one subordinate's region); WRAP loops within its section = WRAP confined to its aligned block (matching the cache line, staying with one subordinate); INCR runs straight, could leave = INCR can cross boundaries, needing the don't-cross rule. The alignment is what makes the sections correspond cleanly to cache lines and subordinate regions.

Watch a WRAP burst confined at the boundary:

The model's lesson: WRAP loops within its aligned section — it wraps at the boundary, never crossing into the next block (the next cache line / subordinate). In the waveform, the address reaches 0x201C and wraps at the 0x2020 boundary back to 0x2000, never touching 0x2020. The aligned boundary confines the burst — matching a cache line and keeping the decode on one subordinate.

4. Real Hardware Perspective

In hardware, the aligned boundary is a direct consequence of the wrap being on the low address bits (chapter 8.7): wrapping the low log2(B) bits while fixing the high bits means the burst stays within the aligned block whose base is those high bits — the alignment is automatic from the bit-level wrap.

Recall the bit-level view (chapter 8.7): WRAP fixes the high address bits (the aligned base) and wraps the low log2(B) bits. The high bits being fixed is the alignment: the block's base is start & ~(B−1), which is aligned to B (its low bits are zero). And the low bits wrapping is the confinement: they cycle through 0 to B−1 (the in-block offsets) and never affect the high bits, so the address never leaves the block. So the aligned confinement isn't extra logic — it falls directly out of wrapping the low bits and fixing the high bits. The hardware that wraps the low bits automatically confines the burst to the aligned block. This is why WRAP's alignment is exact and free: it's the bit-level wrap viewed structurally.

The cache-line match is hardware-exact because both use the same alignment. A cache line of size B is aligned to B — its address has the low log2(B) bits as the in-line offset and the high bits as the tag/index. A WRAP burst of block size B has the same split: low log2(B) bits wrap (the in-block offset = in-line offset), high bits fixed (the aligned base = the line's tag/index bits). So the WRAP block and the cache line are the same aligned region with the same bit split. This is why WRAP fills exactly one cache line: the burst's aligned block is the cache line. The hardware alignment of caches and the hardware alignment of WRAP coincide by construction — both are alignment to B.

The decode stability is hardware-guaranteed when decode regions are aligned (which they are). AHB decode regions are aligned to at least some granularity (conventionally 1KB or larger). Since a WRAP burst's block (size B, at most 64 bytes for a 16-beat word burst) is smaller than and aligned within any decode region (≥1KB), the WRAP block lies entirely within one decode region — so the decode never changes mid-burst. So as long as decode regions are aligned and at least as large as the WRAP block (always true in practice), WRAP's confinement guarantees decode stability automatically. The hardware decoder sees a stable region throughout the WRAP burst. INCR, lacking this confinement, requires the manager to ensure it doesn't cross a region — the don't-cross-1KB-boundary guideline.

A hardware note on the 1KB boundary specifically: the convention that bursts shouldn't cross a 1KB boundary comes from 1KB being a common minimum decode-region size in AHB systems — so staying within a 1KB-aligned region guarantees staying within one subordinate. (AXI later formalized a stricter 4KB-boundary rule for the same decode-stability reason.) For WRAP, this is automatic (its block is ≤64 bytes, far smaller than 1KB, and aligned). For INCR, the manager must enforce it — breaking a long INCR burst at 1KB-aligned boundaries so each piece stays within one subordinate's region. So the 1KB rule is an INCR concern; WRAP satisfies it trivially by its aligned confinement.

5. System Architecture Perspective

At the system level, the aligned wrap boundary is what makes WRAP safe and self-contained — it requires no boundary management — while INCR's boundary-crossing potential is a system constraint the manager and interconnect must enforce.

WRAP's self-containment simplifies the system: because a WRAP burst is confined to its aligned block (smaller than any decode region), the system never has to worry about a WRAP burst crossing a subordinate boundary or a cache-line boundary — it's safe by construction. So WRAP bursts "just work" with respect to boundaries: the interconnect routes them to one subordinate (the decode is stable), and they fill exactly one cache line. This self-containment is a real architectural convenience — WRAP needs no boundary-management logic. It's one less thing for the system to handle, which is part of why WRAP is the clean choice for cache fills (its natural use).

INCR's boundary-crossing potential is a system constraint that must be enforced. Because INCR increments linearly and can cross decode boundaries, the manager (or interconnect) must ensure an INCR burst doesn't cross into another subordinate's region — typically by breaking the burst at decode boundaries (the don't-cross-1KB-boundary guideline). So a DMA engine issuing long INCR transfers must split them at 1KB-aligned boundaries so each sub-burst stays within one subordinate. This is real logic the system implements: boundary-aware burst splitting for INCR. So INCR's flexibility (any-length linear) comes with the cost of boundary management, which WRAP avoids. The system handles INCR's boundary crossing explicitly; WRAP's is automatic.

The deeper architectural point is that the aligned boundary reflects a fundamental alignment principle: structures that must be treated atomically (cache lines, decode regions) are naturally aligned to their size, and confining accesses to aligned blocks (as WRAP does) keeps those structures intact. This is why the wrap boundary is aligned and why the decode-boundary rule exists: both enforce that bursts respect the natural alignment of the structures they touch. WRAP enforces it by construction (confined to an aligned block); INCR requires explicit enforcement (don't cross the aligned decode boundary). So the boundary behavior is an instance of the broader principle that aligned structures require aligned access patterns — a principle that recurs throughout memory-system design (and that AXI's 4KB-boundary rule continues). Understanding the wrap boundary this way connects it to the general importance of alignment in system architecture.

6. Engineering Tradeoffs

The aligned wrap boundary embodies the confine-to-aligned-block design.

• WRAP (auto-confined) vs INCR (must manage). WRAP's aligned confinement makes it safe by construction (no boundary management, matches cache lines, decode stable) at the cost of being restricted to one aligned block. INCR is flexible (any-length linear) but must be managed to not cross boundaries. WRAP for confined cache-line-aligned access, INCR for flexible linear access with boundary care.
• Aligned boundary vs arbitrary. The boundary being at the naturally-aligned block size makes WRAP match cache lines and decode regions exactly. An arbitrary boundary wouldn't align with these structures. The alignment is essential for WRAP's purpose.
• Automatic vs explicit boundary safety. WRAP gets boundary safety automatically (from its aligned confinement); INCR requires explicit enforcement (boundary-aware splitting). The automatic case is simpler but restricted; the explicit case is flexible but needs logic.
• The 1KB convention. The don't-cross-1KB-boundary rule reflects the minimum decode-region granularity, keeping the rule simple (one boundary to respect). A finer rule would be more permissive but complex. The 1KB convention is a simple, safe granularity.

The throughline: the wrap boundary sits at the naturally-aligned block of size B = L × s, confining a WRAP burst to one aligned block. This confinement — automatic from wrapping the low address bits — is what makes WRAP match cache lines (also aligned) and stay within one subordinate's decode region (decode stable), with no boundary management needed. INCR, unconfined, requires the explicit don't-cross-a-decode-boundary (1KB) rule. The aligned boundary is the structural foundation of WRAP's usefulness: it confines bursts to the naturally-aligned blocks that cache lines and decode regions occupy.

7. Industry Example

Trace the boundary behavior for WRAP and INCR.

A system has subordinates at aligned regions, a CPU doing cache fills (WRAP), and a DMA doing long linear transfers (INCR).

• A cache fill — WRAP, auto-confined. The CPU fills a 32-byte cache line with a WRAP8 burst. The burst is confined to the aligned 32-byte block (the cache line), wrapping at the 32-byte boundary. It never crosses into the next cache line or another subordinate's region — the confinement is automatic. The decode stays on the memory subordinate throughout. No boundary management needed; WRAP just fills the one aligned line.
• A DMA transfer — INCR, boundary-managed. The DMA engine moves a large buffer with INCR bursts. Because INCR increments linearly and could cross a decode boundary, the DMA breaks the transfer at 1KB-aligned boundaries: each INCR sub-burst stays within one 1KB-aligned region (one subordinate). So a transfer spanning a 1KB boundary becomes two INCR bursts, one on each side. The DMA's boundary-aware splitting ensures each burst stays with one subordinate.
• A bug avoided. Suppose the DMA didn't split at boundaries and issued one long INCR burst across a 1KB decode boundary. The beats before the boundary would address subordinate A; the beats after would address subordinate B — but the burst was set up for A. The result: corrupted transfer (the post-boundary beats hit the wrong subordinate, possibly erroring or writing wrong data). The boundary-aware splitting prevents this. WRAP would never have this issue (it's confined).
• The alignment connection. The cache line (32-byte, aligned), the WRAP8 block (32-byte, aligned), and the decode regions (1KB-aligned) all respect natural alignment. The WRAP block fits within a cache line and within a decode region (both aligned, both ≥ the WRAP block). So WRAP's aligned confinement keeps it within both — the alignment principle in action. INCR, unconfined, must be explicitly kept within the decode region.
• Why WRAP for cache fills, INCR for DMA. The cache fill uses WRAP precisely because it needs to fill one aligned line and stay confined — WRAP's aligned boundary delivers this. The DMA uses INCR for flexible linear movement, accepting the boundary-management cost. So the boundary behavior reinforces the type choice: WRAP for confined aligned access (cache fills), INCR for flexible linear access (DMA, with boundary care).

The example shows the boundary behavior in practice: WRAP's automatic confinement (cache fills never cross boundaries) versus INCR's required boundary management (DMA splits at 1KB boundaries), with the alignment principle connecting cache lines, WRAP blocks, and decode regions. The boundary rule (don't cross a decode boundary) is an INCR concern that WRAP satisfies by construction.

8. Common Mistakes

9. Interview Insight

Boundary wrapping is a discriminating interview topic — connecting WRAP's aligned confinement to both cache lines and decode stability is the signal.

The answer that lands connects the aligned boundary to its two purposes: "A WRAP burst wraps at a boundary that's naturally aligned to the block size B, which is the beat count times the beat size — so the burst is confined to exactly one aligned B-byte block. This alignment is the key. First, it matches a cache line: a cache line is also naturally aligned to its size, so the WRAP block is the cache line — same alignment, same address-bit split — which is why WRAP fills exactly one line and serves cache fills. Second, it gives decode stability: because the WRAP block is small and aligned, it lies within one decode region, so the burst never crosses into another subordinate's region. INCR, by contrast, increments linearly and could cross a decode boundary, changing the selected subordinate mid-burst — which is broken — so there's a guideline that bursts must not cross a 1KB boundary, and managers split long INCR bursts at decode boundaries. WRAP satisfies that automatically; INCR must be managed." The aligned-confinement-matches-cache-lines point, the decode-stability point, and the INCR-must-not-cross-1KB rule are the senior signals.

10. Practice Challenge

Reason from the aligned boundary.

1. Locate the boundary. State where a WRAP8 of words wraps and the block it's confined to.
2. The alignment. Explain why the boundary is at B = L × s and naturally aligned.
3. Cache-line match. Explain why a WRAP burst's block equals a cache line of the same size.
4. Decode stability. Explain why WRAP never crosses a decode boundary but INCR can.
5. The INCR rule. State the boundary rule for INCR and how a manager enforces it.

11. Key Takeaways

• The wrap boundary is at the naturally-aligned block of size B = L × s — a WRAP burst is confined to exactly one aligned B-byte block, wrapping at its boundaries.
• The aligned confinement is automatic from wrapping the low log2(B) bits and fixing the high bits (chapter 8.7) — no extra logic.
• It matches a cache line — a cache line is also aligned to its size with the same bit split, so the WRAP block is a cache line of size B. This is why WRAP serves cache fills.
• It gives decode stability — the small aligned WRAP block lies within one decode region, so WRAP never crosses into another subordinate's region (automatic).
• INCR can cross boundaries (it increments linearly) — so the guideline is bursts must not cross a 1KB decode boundary, and managers split long INCR bursts at decode boundaries. WRAP satisfies this automatically.
• The aligned boundary reflects a general principle — atomic structures (cache lines, decode regions) are naturally aligned to their size, and confining bursts to aligned blocks keeps them intact (a principle AXI continues with its 4KB rule).

12. What Comes Next

You now understand the wrap boundary deeply. The next chapter covers the beat size that scales these calculations:

• 8.9 — Beat Size (coming next) — how HSIZE sets the per-beat byte count and the burst footprint.

To revisit the burst types and address math, see WRAP4 & INCR4, WRAP8 & INCR8, WRAP16 & INCR16, and Burst Address Calculation; for the overview, Burst Overview. For the decode this stays within, see HSEL. For the broader protocol map, see the AMBA family overview.