Lab-paced video lessons you can code along to.
Each lesson ends with a working artifact — RTL, testbench, regression scripts — that you can fork directly into your repo.
Enroll in a video course
Video courses use the same one-step enrollment as every VLSI Mentor product — pay offline, submit a request, and get access the moment an admin approves.
Verilog Video Course
Lab-paced Verilog RTL video walkthroughs — write the RTL, build the testbench, run the regression.
RTL Foundations
Modeling, simulation intent, lint discipline, and the structure of synthesizable Verilog.
Watch the seriesSystemVerilog for Verification
Classes, randomization, assertions, coverage — the language modern DV is written in.
Watch the seriesUVM From Zero
Agent, sequencer, driver, monitor, scoreboard — the reusable VIP shape, end to end.
Watch the seriesAMBA AXI Deep Dive
Channels, handshakes, ordering rules, outstanding transactions, exclusive access.
Watch the seriesPCIe Verification
TLPs, DLLPs, LTSSM, and the test plan structure for an endpoint or root complex.
Watch the seriesDDR Bring-Up
Bank groups, training, refresh, and the timing margins that decide whether your SoC boots.
Watch the series