AMBA AHB · Module 12

Single-Master Simplification

Exactly what drops out of AHB when there's only one master — signal by signal. The arbitration signals (HBUSREQ, HGRANT, HMASTER, HLOCK, HSPLIT) and the SPLIT/RETRY responses are removed; every transfer signal (HADDR, HWRITE, HSIZE, HBURST, HTRANS, HREADY, HRESP, data) stays. The master drives directly, so its interface shrinks.

Chapter 12.1 established why AHB-Lite exists; this chapter is the precise, signal-by-signal account of what the single-master assumption removes — and, just as importantly, what it keeps. The rule is exact: remove everything whose meaning depends on there being more than one master; keep everything about the data transfer itself. Removed: the arbitration signals — HBUSREQ, HGRANT (request/grant), HMASTER (which master), HLOCK/HMASTLOCK (locking out other masters), HSPLIT (split-completion bitmap) — and the SPLIT and RETRY responses (so HRESP narrows from four codes to just OKAY/ERROR). Kept: every transfer signal — HADDR, HWRITE, HSIZE, HBURST, HTRANS, HPROT, HWDATA, HRDATA, HREADY, HRESP, HSEL. The master's interface shrinks (no request/grant/lock outputs; it drives directly). This chapter walks the signal list, the master-interface simplification, and the principle that nothing about the transfer changes — only the multi-master coordination is stripped.

1. What Is It?

The single-master simplification is the exact set of removals (and the things kept) when AHB is reduced to one master. The dividing principle: does this signal/feature only make sense with multiple masters?

Removed — arbitration signals: HBUSREQ, HGRANT, HMASTER, HLOCK/HMASTLOCK, HSPLIT.
Removed — responses: SPLIT and RETRY (HRESP narrows to OKAY/ERROR only).
Kept — transfer signals: HADDR, HWRITE, HSIZE, HBURST, HTRANS, HPROT, HWDATA, HRDATA, HREADY, HRESP, HSEL.
Changed — master interface: the master drives the bus directly (no request/grant/lock), so those interface signals disappear.

Figure 1 — signals kept vs removed. Kept (left): the transfer signals — HADDR, HWRITE/HSIZE/HBURST, HTRANS, HPROT, HWDATA/HRDATA, HREADY, HRESP, HSEL — the full pipelined transfer, untouched. Removed (right): the arbitration signals — HBUSREQ, HGRANT, HMASTER, HLOCK/HMASTLOCK, HSPLIT — and the SPLIT/RETRY response codes (HRESP narrows from four codes to OKAY/ERROR). All the removed items exist only to coordinate multiple masters.

So the single-master simplification is a clean partition of AHB's signals into "transfer" (kept) and "arbitration" (removed). Every removed signal answers a multi-master question — who requests (HBUSREQ), who's granted (HGRANT), which master (HMASTER), lock out whom (HLOCK), split which master (HSPLIT), release the bus to whom (SPLIT/RETRY). Every kept signal is about the transfer — what address (HADDR), read or write (HWRITE), what size/burst/type (HSIZE/HBURST/HTRANS), the data (HWDATA/HRDATA), ready/response (HREADY/HRESP). So the simplification is exactly the removal of the multi-master partition, leaving the transfer partition intact. So it's a precise, principled subset.

2. Why Does It Exist?

The single-master simplification takes this exact form because each removed signal encodes a multi-master concept that becomes vacuous with one master, and each kept signal encodes a transfer property that's independent of master count — so the partition between them is principled, not arbitrary.

The removed signals are vacuous with one master — walk through them. HBUSREQ/HGRANT: a master requests the bus and waits for a grant; with one master, it never competes, so it never requests — the request/grant pair encodes "asking permission among competitors," vacuous when you're the only one. HMASTER: identifies which master is driving; with one, the answer is constant (always master 0) — the signal carries no information. HLOCK/HMASTLOCK: marks a sequence as locked so another master can't grab the bus mid-sequence; with one master, no one can interrupt, so every sequence is implicitly atomic — locking is meaningless. HSPLIT: a bitmap a slave uses to tell the arbiter which split master to re-grant; with one master, there's no set of masters to track — vacuous. So each removed signal is the encoding of a multi-master relationship, and a single master makes that relationship trivial/empty. So they're removed because they'd carry no information. So the removals are forced by the single-master assumption, not chosen.

The SPLIT/RETRY responses are vacuous too: both exist to let a slave release the bus to other masters when it can't complete promptly — SPLIT (the slave will signal the arbiter when ready, and the arbiter re-grants) and RETRY (the master should retry, letting others go meanwhile). Both presuppose other masters who benefit from the release. With one master, releasing the bus helps no one (there's no other master to use it) — the slave should just stall the single master directly with wait states (HREADY low). So SPLIT/RETRY add nothing a wait state doesn't already do, and they're removed; HRESP keeps only OKAY (success) and ERROR (failure). So the response simplification follows the same principle. (Chapter 12.4 details the simplified responses.)

The kept signals are master-count-independent: HADDR (the address), HWRITE (direction), HSIZE/HBURST/HTRANS (size/burst/type), HPROT (protection), HWDATA/HRDATA (data), HREADY (wait/complete), HRESP (OKAY/ERROR), HSEL (which slave) — none of these depends on how many masters exist. They describe a transfer between the master and a slave — equally meaningful with one master or many. So they're kept unchanged. So the simplification exists in this exact form because the multi-master signals become vacuous (forced removal) while the transfer signals are master-count-independent (kept) — a principled, not arbitrary, partition. The single assumption "one master" cleanly determines the entire subset. (And the master interface shrinks as a consequence: with no request/grant/lock to drive, those master outputs/inputs disappear.)

3. Mental Model

Model the single-master simplification as converting a multi-tenant office's shared facilities to a single-tenant building — you remove the badge-access turnstiles, the room-booking system, the "occupied" door signs, and the front-desk roster (all the sharing infrastructure), but you keep every office, desk, outlet, and the elevator (all the working infrastructure) — because when one tenant occupies the whole building, there's no one to share with, but the work itself is unchanged.

A multi-tenant office building (full AHB) has two kinds of infrastructure. Sharing infrastructure coordinates the multiple tenants: badge turnstiles gating who enters (request/grant), a room-booking system assigning shared rooms (the arbiter), "occupied" door signs reserving a room exclusively (locks), a front-desk roster tracking who's in (HMASTER), and a "we'll call you back" waitlist when a room's busy (SPLIT/RETRY). Working infrastructure is what actually lets work happen: the offices, desks, outlets, network, elevator (the transfer signals — address, data, control, ready). Now convert to a single-tenant building (AHB-Lite): one tenant occupies everything. You remove all the sharing infrastructure — no turnstiles (you're the only one entering), no booking system (every room is yours), no occupied signs (no one to exclude), no roster (it's always you), no waitlist (no one waiting). But you keep all the working infrastructure — every office, desk, outlet, elevator — because the work is identical; only the sharing is gone. The building functions exactly as well for its one tenant, minus the now-pointless coordination.

This captures the simplification: the multi-tenant building = full AHB; single-tenant = AHB-Lite; badge turnstiles = HBUSREQ/HGRANT; room-booking system = the arbiter; occupied signs = HLOCK; front-desk roster = HMASTER; the waitlist = SPLIT/RETRY; offices/desks/outlets/elevator = the transfer signals (HADDR, data, HTRANS, HREADY, …). Remove the sharing infrastructure (vacuous for one tenant), keep the working infrastructure (unchanged) — same productive building, no coordination overhead.

Watch an AHB-Lite burst — every transfer feature is retained:

AHB-Lite INCR4 burst — full transfer features kept

5 cycles

Figure 2 — an AHB-Lite INCR4 burst: all transfer features retained. The master drives a 4-beat incrementing burst — HTRANS = NONSEQ for the first beat then SEQ for the rest, HBURST = INCR4, HSIZE = WORD, addresses incrementing A, A+4, A+8, A+12. HREADY paces the data, HRESP = OKAY. None of this needs arbitration — bursts, sizes, transfer types, and wait states are all kept in AHB-Lite, identical to full AHB.

The model's lesson: convert to single-tenant — remove the sharing infrastructure, keep all the working infrastructure. In the waveform, the full burst protocol (HTRANS, HBURST, HSIZE, HREADY, HRESP) is intact — only the arbitration signals are gone.

4. Real Hardware Perspective

In hardware, the simplification shows up as removed wires and removed logic blocks: the request/grant network and arbiter disappear, HMASTER routing vanishes, lock logic is gone, slaves lose SPLIT/RETRY machinery, and the master loses its arbitration-handshake logic.

The removed wiring is concrete: in full AHB, every master has an HBUSREQ output and HGRANT input wired to the arbiter, an HLOCK output, and the system carries HMASTER (and HMASTLOCK) to slaves; split-capable slaves drive HSPLIT back to the arbiter. In AHB-Lite, all those wires are gone — no HBUSREQ/HGRANT net, no HMASTER bus, no HLOCK, no HSPLIT. So the physical signal count drops. So in hardware, the simplification removes a whole class of interconnect wiring.

Figure 3 — the master interface simplifies. A full AHB master has, beyond the transfer signals, an HBUSREQ output (request the bus), an HGRANT input (wait to be granted), and an HLOCK output (lock the bus) — and must wait for HGRANT before driving. An AHB-Lite master drops HBUSREQ, HGRANT, and HLOCK, and drives the bus directly without waiting for a grant. So the interface is smaller and the control logic simpler, because the master always owns the bus.

The removed logic blocks are the bigger saving: the arbiter (priority/round-robin logic, grant generation) is deleted entirely. The master-side request/grant state machine (the logic that asserts HBUSREQ, waits for HGRANT, and only then drives) is gone — the AHB-Lite master just drives. The lock-handling logic (asserting/honoring HLOCK) is gone. On the slave side, SPLIT/RETRY machinery — the logic to issue a SPLIT/RETRY, the bookkeeping a SPLIT slave needs (tracking which master to signal via HSPLIT) — is deleted (chapter 12.6). So entire logic blocks vanish, not just wires. So in hardware, the simplification deletes the arbiter, the master's handshake FSM, lock logic, and slave SPLIT/RETRY machinery — substantial area and complexity.

The interconnect collapse ties it together (chapter 12.1): with no arbiter and no master-side muxing (one master drives directly), the interconnect reduces to a decoder + read-data/response mux. The address/control path is a direct broadcast from the one master to all slaves (no mux). Only the return path (slave → master) needs a mux (selecting the active slave's HRDATA/HREADY/HRESP). So the hardware interconnect is minimal. So in hardware, the single-master simplification removes wires (HBUSREQ/HGRANT/HMASTER/HLOCK/HSPLIT), removes logic blocks (arbiter, handshake FSM, lock logic, SPLIT/RETRY machinery), and collapses the interconnect to decode + return-mux — all while the transfer datapath (address/control broadcast, data buses, HREADY/HRESP handling) is identical to full AHB. So the hardware is dramatically leaner with no change to transfer behavior.

5. System Architecture Perspective

At the system level, the single-master simplification's value is concentrated in three areas — area/power, timing, and especially verification — and understanding which removals drive which savings clarifies why AHB-Lite is so attractive.

The area and power savings come from the deleted logic: no arbiter, no per-master request/grant logic, no lock logic, no SPLIT/RETRY machinery, simpler slaves, a simpler master, and a decode-plus-mux interconnect instead of a full arbitrated one. Across a design with several slaves, this is meaningful silicon saved — and less logic means less dynamic and leakage power. So at the system level, the simplification directly reduces area and power. For cost- and power-sensitive parts (microcontrollers), this matters.

The timing benefit is subtler but real: in full AHB, the arbiter sits in the address-phase path (it must grant before the master drives, and HMASTER/grant signals fan out), and the master-side mux adds delay. Removing the arbiter and master mux shortens the critical path around bus access — the single master drives directly, no grant-wait, no arbiter delay. So AHB-Lite can often clock higher or meet timing more easily. So at the system level, the simplification eases timing closure. (The transfer datapath timing is unchanged, but the access path is shorter.)

The verification saving is often the decisive one: multi-master arbitration is a notorious source of complexity and bugs — arbitration fairness, grant timing, lock/unlock corner cases, SPLIT/RETRY interactions, master-priority scenarios, handover races, starvation. Verifying all of this is a large effort, and bugs here are subtle and hard to find. The single-master simplification eliminates this entire category: with one master, there are no arbitration scenarios to verify — no fairness, no grant races, no lock corners, no SPLIT/RETRY, no starvation. The verification scope collapses to the transfer protocol and the slaves. So at the system level, the simplification dramatically reduces verification effort and risk — frequently the biggest practical win, because verification dominates SoC schedules and arbitration is among the hardest parts to verify. So the single-master simplification's system value is: less area/power (deleted logic), easier timing (no arbiter in the access path), and much less verification (the entire arbitration category gone). The verification saving alone often justifies choosing AHB-Lite wherever a single master suffices — you don't just save gates, you save the hardest verification work. This is why AHB-Lite is the default for single-master designs: the simplification removes precisely the parts that are expensive to build, hard to time, and hardest to verify, while leaving the valuable transfer engine fully intact. So at the system level, the single-master simplification is a high-leverage right-sizing that pays off most in verification.

6. Engineering Tradeoffs

The single-master simplification embodies the principled-subset design.

Principled partition vs ad-hoc stripping. Removing exactly the multi-master-dependent signals (a principled partition) gives a clean, interoperable subset (AHB-Lite), versus ad-hoc removal that might break the transfer or interoperability. The principle (remove what needs more than one master) defines the subset precisely.
Removed logic (arbiter, handshake, lock, SPLIT/RETRY) vs kept datapath. Deleting the arbitration logic saves area/power/timing/verification; keeping the full transfer datapath preserves performance. The split maximizes savings with no transfer-performance loss.
Wait states vs SPLIT/RETRY. A single-master slave stalls the master with wait states (HREADY low) — simple and sufficient — instead of SPLIT/RETRY (which only help by releasing the bus to other masters). So the response set shrinks to OKAY/ERROR with no loss for one master.
Verification scope: transfer-only vs transfer+arbitration. AHB-Lite's verification covers only the transfer and slaves; full AHB adds the large, bug-prone arbitration category. The simplification's biggest practical payoff is this reduced verification scope.

The throughline: the single-master simplification removes exactly the signals/features whose meaning depends on more than one master — HBUSREQ, HGRANT, HMASTER, HLOCK/HMASTLOCK, HSPLIT, and the SPLIT/RETRY responses (HRESP → OKAY/ERROR) — and keeps every transfer signal (HADDR, HWRITE, HSIZE, HBURST, HTRANS, HPROT, data, HREADY, HRESP, HSEL). The master drives directly (smaller interface). In hardware it deletes wires and whole logic blocks (arbiter, handshake FSM, lock, SPLIT/RETRY) and collapses the interconnect to decode + return-mux. The savings concentrate in area/power, timing, and — most decisively — verification, with zero transfer-performance loss.

The single master still uses HREADY wait states — removing SPLIT/RETRY doesn't remove the ability to stall

A point that prevents confusion about the removed SPLIT/RETRY: removing SPLIT and RETRY does not remove a slave's ability to stall the master — that's done with HREADY wait states, which AHB-Lite keeps. It's easy to think "if SPLIT/RETRY are gone, how does a slow slave handle a transfer it can't complete immediately?" The answer: the same way any AHB slave handles needing more time — it drives HREADY low, inserting wait states that stretch the transfer until it's ready, then drives HREADY high to complete. Wait states are part of the transfer protocol (kept in AHB-Lite), entirely separate from SPLIT/RETRY (arbitration responses, removed). The distinction is why the slave stalls: with multiple masters, a slave facing a long delay might use SPLIT/RETRY to release the bus so other masters can proceed during the wait — a multi-master optimization. With one master, there are no other masters to hand the bus to, so releasing it helps no one; the slave simply holds the single master with wait states until ready. This is simpler and loses nothing (the single master had nothing better to do anyway — it can't issue to a different slave while waiting, as there's no concurrency). So AHB-Lite slaves stall with HREADY wait states, exactly as full-AHB slaves do for short delays — they just can't (and needn't) use SPLIT/RETRY to release the bus. So a slow AHB-Lite slave (e.g. a flash controller fetching data) inserts wait states freely; the simplification removes only the bus-release mechanism, not the stall mechanism. Don't conflate "removed SPLIT/RETRY" with "can't stall" — HREADY wait states remain the universal stall mechanism.

7. Industry Example

See the simplification concretely in a single-master design.

A microcontroller's AHB-Lite bus connects one CPU to flash, SRAM, and an APB bridge.

The signal list. The bus carries HADDR, HWRITE, HSIZE, HBURST, HTRANS, HPROT, HWDATA, HRDATA, HREADY, HRESP, and per-slave HSEL — the full transfer set. It does not carry HBUSREQ, HGRANT, HMASTER, HLOCK, or HSPLIT — there's no arbiter to wire them to.
The CPU drives directly. The CPU's bus interface drives HADDR/HTRANS/etc. straight onto the bus every cycle it has a transfer — no HBUSREQ assertion, no waiting for HGRANT. Its interface has no request/grant/lock pins. So the CPU's bus logic is simpler.
A slow flash access uses wait states. When the CPU fetches from flash that needs extra cycles, the flash controller drives HREADY low for the wait states, then high — stalling the CPU directly. It does not (and cannot) SPLIT or RETRY; with one master, wait states are the right and only stall mechanism. HRESP is OKAY (or ERROR on a fault).
A burst still works fully. The CPU issues an INCR4 burst to SRAM — NONSEQ then three SEQ beats, HBURST = INCR4, incrementing addresses — exactly as on full AHB. Bursts, sizes, and transfer types are all retained.
The interconnect. The interconnect is a decoder (HADDR → HSEL for flash/SRAM/bridge) plus a read-data/response mux (selecting the active slave's HRDATA/HREADY/HRESP back to the CPU). There's no arbiter, no master mux.
Verification focus. The team verifies the transfer protocol (pipeline, bursts, wait states, OKAY/ERROR) and each slave's behavior. They do not verify arbitration, grant timing, locks, or SPLIT/RETRY — those don't exist. The verification plan is markedly smaller.

The example shows the simplification end-to-end: the arbitration signals and logic are absent, the transfer signals and full transfer behavior (bursts, wait states, responses) are present, the master drives directly, the interconnect is decode + mux, and verification is transfer-focused. This is what "single-master simplification" looks like in a shipping MCU.

8. Common Mistakes

Single-master-simplification misconceptions

"AHB-Lite removes bursts / wait states / data sizes." No — those are transfer features, all kept. Only the arbitration signals and SPLIT/RETRY are removed.
"Without SPLIT/RETRY, a slow slave can't stall." No — it stalls with HREADY wait states (kept). SPLIT/RETRY only mattered for releasing the bus to other masters.
"HMASTER is still there, just tied to 0." It's removed — there's no other master to distinguish, so the signal is dropped entirely (not merely tied off in the protocol).
"The master still requests the bus." No — the AHB-Lite master has no HBUSREQ/HGRANT; it drives the bus directly, always owning it.
"HRESP still has four codes." No — it narrows to OKAY/ERROR (SPLIT/RETRY removed).
"The simplification changes the transfer timing." No — the transfer datapath/timing is identical; only the access (arbitration) path is removed, and the master interface shrinks.

9. Interview Insight

The single-master simplification is a precise interview topic — the kept/removed partition and the principle behind it are the signals.

Figure 4 — a strong answer in one card: removed are HBUSREQ, HGRANT, HMASTER, HLOCK, HSPLIT and the SPLIT/RETRY responses (HRESP → OKAY/ERROR); kept are all the transfer signals (HADDR, HWRITE, HSIZE, HBURST, HTRANS, HPROT, data, HREADY, HRESP, HSEL); the master drives directly, so its interface shrinks. The senior point: remove exactly what depends on more than one master; the data transfer itself is unchanged.

The answer that lands states the principle and the partition: "The single-master simplification removes exactly the signals and features whose meaning depends on there being more than one master, and keeps everything about the transfer itself. Removed are the arbitration signals — HBUSREQ and HGRANT (the request/grant handshake), HMASTER (which master is active), HLOCK (locking out other masters), and HSPLIT (the split-completion bitmap) — plus the SPLIT and RETRY responses, so HRESP narrows from four codes to just OKAY and ERROR. Kept are all the transfer signals: HADDR, HWRITE, HSIZE, HBURST, HTRANS, HPROT, the write and read data buses, HREADY, HRESP, and the per-slave HSEL. Each removed signal answers a multi-master question — who requests, who's granted, which master, lock out whom, release the bus to whom — that's vacuous with one master. Each kept signal describes the transfer, which doesn't depend on master count. The master also drives the bus directly, with no request/grant/lock logic, so its interface shrinks. Critically, a slow slave still stalls with HREADY wait states — removing SPLIT/RETRY doesn't remove the ability to stall, just the ability to release the bus to other masters, which there aren't. The savings are in area, power, timing, and especially verification — the whole arbitration category disappears." The principled partition (remove multi-master-dependent, keep transfer) and the wait-states-remain point are the senior signals.

🔍 The discriminator: the partition is principled — remove exactly what's vacuous with one master, keep the master-count-independent transfer

The discriminator on the single-master simplification is whether you can state the principle that defines the partition — and apply it to justify each removal — rather than just reciting a list. A weak answer lists "no arbiter, no grant." A solid answer gives the full removed set (HBUSREQ, HGRANT, HMASTER, HLOCK, HSPLIT, SPLIT/RETRY) and the kept set (the transfer signals). But the senior answer states the rule: remove exactly the signals/features whose meaning depends on more than one master (they become vacuous with one), and keep everything that's master-count-independent (the transfer). Then it applies the rule per signal: HBUSREQ/HGRANT encode competing for the bus (no competition → vacuous); HMASTER identifies which of several (only one → no information); HLOCK excludes other masters (none to exclude → automatic atomicity); HSPLIT tracks which master to re-grant (no set of masters → vacuous); SPLIT/RETRY release the bus to others (none waiting → pointless). The crucial nuance is the wait-states-remain point: removing SPLIT/RETRY does not remove stalling — HREADY wait states (a transfer feature) stay; SPLIT/RETRY only added bus-release-to-others, which is meaningless with one master. The flourish is where the savings land: area/power (deleted logic), timing (no arbiter in the access path), and decisively verification (the entire arbitration category — fairness, grant races, lock corners, SPLIT/RETRY, starvation — gone). A candidate who articulates the principled partition, justifies each removal by its multi-master dependence, and notes that wait states still handle stalling demonstrates they understand the structure of AHB (transfer vs arbitration layers), not just a memorized subset.

10. Practice Challenge

Reason from the single-master simplification.

The partition. State the principle that decides what's removed vs kept, and list each side.
Justify removals. For HBUSREQ/HGRANT, HMASTER, HLOCK, and SPLIT/RETRY, explain why each is vacuous with one master.
Read the waveform. From Figure 2, identify the transfer features present in the AHB-Lite burst and confirm no arbitration signals appear.
Stalling. Explain how a slow AHB-Lite slave stalls the master without SPLIT/RETRY.
Savings. Explain where the simplification's savings come from (area/power, timing, verification) and which is usually decisive.

11. Key Takeaways

The single-master simplification removes exactly the multi-master-dependent signals/features — HBUSREQ, HGRANT, HMASTER, HLOCK/HMASTLOCK, HSPLIT, and the SPLIT/RETRY responses (HRESP → OKAY/ERROR) — and keeps every transfer signal (HADDR, HWRITE, HSIZE, HBURST, HTRANS, HPROT, data, HREADY, HRESP, HSEL).
The principle is exact: remove what's vacuous with one master (competing, identifying, excluding, releasing-to-others); keep what's master-count-independent (the transfer itself).
The master drives directly — no HBUSREQ/HGRANT/HLOCK, no grant-wait — so its interface and control logic shrink.
A slow slave still stalls with HREADY wait states — removing SPLIT/RETRY removes only the bus-release-to-others mechanism, not the ability to stall.
In hardware it deletes wires and logic blocks — the arbiter, the master handshake FSM, lock logic, and slave SPLIT/RETRY machinery — and collapses the interconnect to decode + return-mux.
The savings are in area/power, timing, and (most decisively) verification — the entire arbitration category (fairness, grant races, locks, SPLIT/RETRY, starvation) disappears, with zero transfer-performance loss.

12. What Comes Next

You now have the precise, signal-by-signal account of the single-master simplification. The next chapters drill into specific removals and the slave design:

Removed Arbitration (next) — why AHB-Lite needs no arbiter or request/grant, in detail.
Simplified Responses — the narrowing to OKAY/ERROR (no SPLIT/RETRY).
AHB-Lite Slave Design — how to build a correct, simpler AHB-Lite slave.

To revisit why AHB-Lite exists, see Why AHB-Lite Exists; for the arbitration machinery being removed, see HBUSREQ & HGRANT and Locked Transfers.