AMBA AHB · Module 11

Address Decoding

How the central AHB decoder maps HADDR to a slave — a single combinational decoder watches the shared address bus, compares its upper bits against the system address map, and asserts exactly one slave's HSEL, so only the addressed slave responds.

This opens Module 11 — Decoder & Slave Selection with the mechanism that routes every transfer to the right place: address decoding. On a shared AHB bus, every slave sees the same HADDR, HWRITE, and HTRANS — so something must decide which slave actually responds. That something is the central decoder: a single combinational block that watches HADDR, compares its upper bits against the system address map, and asserts exactly one slave's HSEL — the slave whose address region contains HADDR. Only the selected slave (HSEL high) responds; the rest ignore the transfer. Decoding runs in the address phase, in parallel with the data phase of the previous transfer (the pipeline), so it costs no extra cycle. This chapter establishes what decoding is and why it's centralized and combinational; the next chapters detail HSEL generation (11.2), the default slave (11.3), and the address map (11.4).

1. What Is It?

Address decoding is the process by which the AHB interconnect determines which slave a transfer is addressed to, by examining HADDR. A single central decoder does this:

It watches HADDR (the shared address bus the active master drives).
It compares HADDR's upper bits against the system address map (each slave's base address and region size).
It asserts exactly one HSEL — the select line of the slave whose region contains HADDR.

Figure 1 — the central decoder. The active master drives HADDR onto the shared bus. A single central decoder watches HADDR, compares it against the address map, and asserts exactly one slave's HSEL (HSEL_0 = 1 here). All slaves see the same HADDR/HWRITE/HTRANS, but only the slave with HSEL high responds — the others ignore the transfer. The decoder is combinational on HADDR.

So decoding answers the question "who is this transfer for?" — and the answer is carried by HSEL. On a shared bus, the address, control, and (for writes) write-data signals are broadcast to all slaves; the decoder's HSEL is what distinguishes the intended recipient from the rest. The selected slave (HSEL high) drives the response (HREADY, HRESP, read data); the unselected slaves (HSEL low) do nothing. So address decoding is the demultiplexing of the shared bus to one target — the routing decision that makes a single shared bus able to serve many slaves.

One central decoder watches HADDR and asserts exactly one slave's HSEL — the addressed slave responds, the rest ignore

Address decoding in one frame: a single central combinational decoder watches the shared HADDR, compares its upper bits against the system address map, and asserts exactly one slave's HSEL — the slave whose address region contains HADDR. All slaves see the same HADDR/HWRITE/HTRANS (broadcast), but only the slave with HSEL high responds (drives HREADY/HRESP/read data); the rest ignore the transfer. Decoding runs in the address phase (no extra cycle — it overlaps the previous transfer's data phase via the pipeline). Only the high-order bits select the region; the low-order bits become the offset within the slave. An unmapped address selects the default slave, so every access has a target. Decoding is how one shared bus routes to many slaves.

2. Why Does It Exist?

Address decoding exists because a shared bus broadcasts to all slaves, so the system needs a mechanism to pick which slave responds — and putting that mechanism in one central decoder (rather than each slave decoding itself) makes the address map a single, consistent, maintainable thing.

The broadcast problem is the root cause: on a shared AHB bus, the master drives one HADDR, and that address bus physically reaches every slave. So every slave sees every address. But only one slave should respond to any given address (each slave owns a distinct region). So there must be a mechanism to tell each slave "this one's for you" or "not for you." That mechanism is decoding → HSEL: the decoder asserts the right slave's HSEL, and each slave responds only when its HSEL is high. So decoding exists to select the one responder from the broadcast — without it, either no slave or multiple slaves would respond, both broken. So decoding exists to demultiplex the shared bus to exactly one target.

The reason decoding is centralized (one decoder for the whole system, not per-slave) is consistency and maintainability of the address map: the address map (which slave owns which region) is a system-level fact. Putting it in one decoder means the map is defined once, in one place — consistent across all slaves, easy to change (re-map a slave by editing the one decoder). If each slave decoded its own address (checking HADDR itself), the address map would be scattered across all slaves — inconsistent risk (two slaves claiming overlapping regions), hard to change (edit every slave), and slaves wouldn't be relocatable (a slave hard-codes its address). So centralizing decoding keeps the address map single-source-of-truth and makes slaves address-agnostic (a slave just responds to HSEL; it doesn't know where it lives). So decoding is centralized for a clean, maintainable, relocatable address map. So decoding exists, centralized, to route the broadcast bus to one target via a single consistent address map.

The reason decoding is combinational (HSEL is a combinational function of HADDR, not registered) is timing: HSEL must be valid in the same address phase as the HADDR it decodes, so the selected slave can sample the address-phase signals and prepare its response. A registered (clocked) decode would delay HSEL by a cycle, misaligning it with HADDR. So decoding is combinational to keep HSEL phase-aligned with HADDR — the slave sees HSEL and HADDR together in the address phase. So decoding exists as a combinational function of HADDR, centralized, to route the shared bus's broadcast to exactly one slave per the system address map.

3. Mental Model

Model address decoding as a mailroom in an apartment building — every letter (transfer) arrives at one mailroom (the decoder), which reads the apartment number (the upper address bits), looks it up on the building directory (the address map), and drops the letter in exactly one mailbox (asserts one HSEL); the apartments themselves don't sort mail — they just check whether their box's flag is up.

In an apartment building, all incoming mail goes to one mailroom (the central decoder). The mailroom reads each letter's apartment number (the upper address bits — the part that identifies which apartment, not the floor-plan detail inside). It looks the number up on the building directory (the address map — which apartment is where). It then drops the letter in exactly one mailbox (asserts one slave's HSEL). Crucially, the apartments (slaves) don't sort mail themselves — they don't read every letter's address; they just check whether their own mailbox flag is up (whether their HSEL is high) and, if so, take the letter (respond). And if a letter has an unknown apartment number (unmapped address), the mailroom puts it in a dead-letter box (the default slave) rather than losing it. So one mailroom, one directory, one mailbox per letter — clean, centralized routing.

This captures decoding: the mailroom = the central decoder; the apartment number (upper bits) = HADDR's high-order bits; the building directory = the address map; dropping in one mailbox = asserting one HSEL; apartments checking their flag, not sorting mail = slaves responding to HSEL, not decoding HADDR themselves; the dead-letter box = the default slave. One mailroom routes every letter to one mailbox per the directory — centralized, consistent, with a fallback.

Watch decoding track HADDR cycle by cycle — combinational, so HSEL changes the same cycle HADDR does:

Combinational decode: HSEL follows HADDR

4 cycles

Figure 2 — decoding is combinational: HSEL tracks HADDR in the same cycle. In cycle 0 HADDR is in slave 0's region, so HSEL_0 is high (HSEL_1 low). In cycle 1 HADDR moves to slave 1's region, so HSEL switches — HSEL_1 high, HSEL_0 low — in the same cycle, no delay. Each address phase decodes to exactly one HSEL. The decode overlaps the previous transfer's data phase (the pipeline), so it costs no extra cycle.

The model's lesson: one mailroom reads the apartment number and drops each letter in one mailbox — the apartments just check their flag. In the waveform, HSEL tracks HADDR combinationally — each address selects exactly one slave, in the same cycle.

4. Real Hardware Perspective

In hardware, the decoder is a small combinational block (comparators or a lookup on HADDR's upper bits) that lives in the interconnect, produces one-hot HSEL lines fanned out to the slaves, and runs entirely within the address phase.

The decoder's logic is a set of address comparisons: for each slave region, the decoder checks whether HADDR's upper bits fall within that region's [base, base+size) range. In practice, when regions are power-of-two aligned and sized, this reduces to comparing a fixed set of high-order HADDR bits against a constant — a cheap equality/range check, often just a few gates per region. So HSEL_n = (HADDR[31:k] matches region n's tag). The decoder ORs nothing — the regions are disjoint, so at most one comparison is true, giving one-hot HSEL. So the decoder is a small, fast combinational comparator bank on HADDR's upper bits.

The HSEL fan-out is the decoder's output: one HSEL line per slave, routed from the decoder to each slave's HSEL input. These are point-to-point (decoder → each slave), unlike the broadcast HADDR/HWRITE/HTRANS. So the slave gets the broadcast address/control plus its dedicated HSEL — and it gates its response on HSEL. So in hardware, the decoder's output is the HSEL bundle, fanned out one-per-slave. (The interconnect also uses the decode to mux the read-data and response signals back from the selected slave to the master — chapter 11.2 and the interconnect chapters detail this return path.)

The address-phase timing is the key constraint: HSEL is combinational on HADDR, so it's valid in the same cycle HADDR is driven (the address phase). The selected slave samples HADDR, HWRITE, HTRANS, and HSEL at the end of the address phase (the rising clock edge), then responds in the data phase. So the decode must settle within the address phase — its combinational delay (comparators + HSEL fan-out) is part of the address-phase timing path. In a large system (many slaves, wide fan-out), this decode path can be timing-critical, sometimes pipelined or buffered — but functionally HSEL is address-phase-aligned. So in hardware, decoding is a combinational comparator bank whose one-hot HSEL output must settle within the address phase, fanned out one line per slave.

A combinational comparator bank on HADDR's upper bits, producing one-hot HSEL, settling within the address phase

The hardware essence: the decoder is a small combinational block in the interconnect. For each slave region it compares HADDR's upper bits against the region's address tag — when regions are power-of-two aligned, this is a cheap constant-comparison (a few gates per region). The regions are disjoint, so at most one comparison is true → one-hot HSEL (exactly one line high). The HSEL lines fan out point-to-point, one per slave (unlike the broadcast HADDR/HWRITE/HTRANS). Because HSEL is combinational on HADDR, it's valid in the same address phase — the selected slave samples HADDR, control, and HSEL together at the clock edge, then responds in the data phase. The decode delay (comparators + fan-out) is part of the address-phase timing path, and can be critical in large systems.

5. System Architecture Perspective

At the system level, address decoding is the realization of the memory map in hardware — it's how the abstract "this peripheral lives at 0x4000_0000" becomes a physical routing decision, and it's the foundation of the whole address-routing fabric.

The memory-map realization is decoding's system role: an SoC has a memory map — a system-level assignment of address ranges to slaves (RAM here, flash there, this peripheral at that base, etc.). The decoder is how that map is enforced in hardware: each region in the map becomes a comparison in the decoder, and the decode asserts the right slave's HSEL. So the decoder is the memory map, in silicon. Change the map (relocate a peripheral) → change the decoder. So decoding ties the software-visible address map to the hardware routing — software reads/writes an address, the decoder routes it to the physical slave at that address. So at the system level, decoding is the bridge between the address map (a system contract) and the physical slaves.

The single-source-of-truth property matters for correctness: because decoding is centralized, the address map is defined once (in the decoder), so there's no risk of two slaves claiming overlapping regions or gaps appearing inconsistently. The system architect defines the map; the decoder enforces it consistently. So centralized decoding gives a coherent address space — every address routes to exactly one place (a real slave or the default slave). So decoding is the guardian of address-space coherence. This is why the address map and the decoder are co-designed: the map is the spec, the decoder is the implementation.

The scalability and fabric view: in a simple system, one decoder routes to a handful of slaves on one shared bus. In a larger system (a multi-layer bus matrix, chapter 12.x / 14.x), decoding happens per layer — each master's path is decoded to route to the right slave, and the matrix can carry multiple transfers concurrently. So decoding is the fundamental routing primitive that scales from a single shared bus to a full interconnect fabric. Every place a transfer must be routed to a slave, a decode happens. So at the system level, decoding is the addressing-and-routing foundation — the realization of the memory map, the guardian of address-space coherence, and the routing primitive that scales across the interconnect fabric. Get the decode (and the map behind it) right, and the whole address space works; get it wrong (overlap, gap, misalignment), and accesses go to the wrong place or nowhere. So decoding is foundational to a correctly functioning SoC address space.

6. Engineering Tradeoffs

Address decoding embodies the centralized-routing design.

Figure 3 — the decode step in four parts: take HADDR (upper bits select the region, lower bits are the in-slave offset); compare it against each region's base..base+size in the address map; find the one region that contains it (regions are disjoint); and assert that slave's HSEL (all others 0). If no region matches, the default slave is selected — so every address selects exactly one target.

Centralized decoder vs per-slave decoding. A central decoder gives a single, consistent, maintainable address map and address-agnostic (relocatable) slaves, at the cost of one central block. Per-slave decoding scatters the map (inconsistency risk, non-relocatable slaves). AHB centralizes the decode.
Combinational vs registered decode. Combinational HSEL is phase-aligned with HADDR (the slave sees them together) at the cost of being in the address-phase timing path. A registered decode would relax timing but misalign HSEL by a cycle. AHB decodes combinationally.
Coarse (high-bits-only) vs fine decode. Decoding on only the upper bits (power-of-two regions) is cheap (few gates) and gives clean offsets, at the cost of coarse region granularity (regions are power-of-two-sized/aligned). Fine decode (arbitrary regions) is flexible but costlier. Most maps use coarse, power-of-two regions.
Decode path vs system size. A small system's decode is fast and non-critical; a large system's decode (many regions, wide HSEL fan-out) can become timing-critical, needing buffering or pipelining. The decode delay scales with system size.

The throughline: address decoding is a single central combinational decoder that watches the shared HADDR, compares its upper bits against the system address map, and asserts exactly one slave's HSEL — demultiplexing the broadcast bus to one target. It's centralized (single-source-of-truth address map, relocatable slaves), combinational (HSEL phase-aligned with HADDR), and high-bits-only (cheap, clean offsets). It realizes the memory map in hardware and is the routing primitive that scales across the interconnect. An unmapped address selects the default slave, so every access has a target.

Address regions must be disjoint and the map complete — overlap gives multi-select, gaps need a default slave

The decoder's correctness rests on two properties of the address map. First, disjoint regions: no two slave regions may overlap, or an address in the overlap would match two comparisons → two HSEL lines high (multi-select) → two slaves driving the response → bus contention and corrupted data. The map must assign each address to at most one slave. Second, completeness via a default: the map need not cover every address (there can be gaps — unmapped regions), but every address must still route somewhere — so the decoder selects the default slave for any address not in a mapped region. Without a default, an unmapped access would assert no HSEL → no slave responds → the master hangs waiting for HREADY (deadlock). So the map must be disjoint (no overlap → one-hot HSEL) and the decode must be total (default slave for gaps → no hang). Designers verify these properties: an overlap check (no two regions intersect) and a coverage check (default slave handles the rest). A decoder built on an overlapping or gap-without-default map is a latent bug — wrong slave selected, contention, or hang.

7. Industry Example

Trace decoding in a small SoC address map.

A system has RAM at 0x0000_0000 (size 256 KB), a UART at 0x4000_0000, a timer at 0x4000_1000, and a default slave for everything else.

The master issues a read to 0x0000_0040 (RAM). The decoder compares the upper bits: 0x0000_0040 falls in RAM's [0x0000_0000, 0x0004_0000) region. So the decoder asserts HSEL_RAM (and no other). The RAM, seeing HSEL high, samples the address-phase signals and prepares to drive the read data in the data phase. The low bits (0x40) are the offset within the RAM. So the read routes to RAM.
The master issues a write to 0x4000_0000 (UART). The decoder compares: 0x4000_0000 matches the UART's region. It asserts HSEL_UART. The UART responds (accepts the write data in the data phase). The RAM and timer, with HSEL low, ignore the transfer. So the write routes to the UART.
The master issues an access to 0x8000_0000 (unmapped). No region contains 0x8000_0000. So the decoder asserts HSEL_DEFAULT (the default slave). The default slave responds — typically with an ERROR response (chapter 11.3 / 11.5) — so the master gets a defined response (an error) rather than hanging. So even the unmapped access has a target.
Two transfers back-to-back (pipelined). While RAM drives its read data (data phase of transfer 1), the decoder is already decoding transfer 2's address (address phase) — the decode overlaps the previous data phase, costing no extra cycle. So decoding keeps pace with the pipeline.

The example shows decoding in action: each address is compared against the map's regions, exactly one HSEL is asserted (the matching slave, or the default for unmapped), and the selected slave responds while the rest ignore the transfer. The high bits select the region, the low bits are the in-slave offset, and the decode overlaps the pipeline. This is how the shared bus routes each access to its target.

8. Common Mistakes

Address-decoding misconceptions

"Each slave decodes its own address." No — a single central decoder decodes HADDR and asserts HSEL; slaves respond to HSEL, they don't compare HADDR themselves. (This keeps the map centralized and slaves relocatable.)
"All the address bits are decoded." Only the upper bits select the region; the lower bits are the offset within the selected slave.
"Decoding takes a cycle." It's combinational — HSEL is valid in the same address phase as HADDR, and it overlaps the previous transfer's data phase (no extra cycle).
"Regions can overlap." No — regions must be disjoint, or an address would select two slaves (multi-select → contention). The map must assign each address to at most one slave.
"An unmapped address selects nothing." It selects the default slave — so the master gets a defined (usually error) response instead of hanging.
"More than one HSEL can be high." No — HSEL is one-hot: exactly one slave (real or default) is selected per transfer.

9. Interview Insight

Address decoding is a foundational interview topic — the centralized/combinational nature, the high-bits-only selection, and the one-hot HSEL with a default are the signals.

Figure 4 — a strong answer in one card: a single central combinational decoder watches HADDR and asserts exactly one slave's HSEL; it compares only the upper bits against the address map (lower bits = offset in the slave); it runs in the address phase; and an unmapped address selects the default slave so every access has a target. The senior point: decoding is centralized, combinational on HADDR, high-bits-only, and one-hot.

The answer that lands explains the mechanism and the why: "On a shared AHB bus, every slave sees the same HADDR — so a single central decoder decides which slave responds. The decoder is combinational: it watches HADDR, compares its upper bits against the system address map, and asserts exactly one slave's HSEL — the slave whose region contains the address. Only that slave responds (drives HREADY, HRESP, read data); the rest, with HSEL low, ignore the transfer. It's centralized so the address map is single-source-of-truth and slaves are relocatable — a slave doesn't know where it lives, it just responds to HSEL. It's combinational so HSEL is valid in the same address phase as HADDR — the slave samples both together at the clock edge. Only the upper bits select the region; the lower bits are the offset within the slave. The regions are disjoint, so HSEL is one-hot — exactly one slave. And an unmapped address selects the default slave, so every access has a target and the master never hangs. The decode overlaps the previous transfer's data phase via the pipeline, so it costs no extra cycle." The centralized-combinational nature, the upper-bits selection, the one-hot HSEL, and the default-slave completeness are the senior signals.

🔍 The discriminator: centralized + combinational + one-hot HSEL with a default — not per-slave decode

The discriminator on address decoding is whether you describe it as a centralized, combinational, one-hot selection — and explain why each property holds. A weak answer says "the address picks the slave." A strong answer gives the mechanism (one central decoder watches HADDR, compares upper bits vs the address map, asserts one HSEL) and the four properties with reasons: centralized (one decoder, not per-slave — so the map is single-source-of-truth and slaves are relocatable/address-agnostic); combinational (HSEL valid in the same address phase as HADDR — the slave samples both together, so the decode is in the address-phase timing path); high-bits-only (upper bits select the region, lower bits are the in-slave offset — cheap power-of-two comparisons); one-hot with a default (disjoint regions → at most one match → exactly one HSEL; unmapped → default slave → every access has a target, no hang). The senior insight is the consequences: centralizing keeps the address map coherent and slaves relocatable; combinational keeps HSEL phase-aligned; disjointness prevents multi-select contention; the default prevents the master hanging on an unmapped access. A candidate who explains decoding as centralized/combinational/one-hot-with-default — and ties each to its consequence (maintainable map, phase alignment, no contention, no hang) — shows they understand decoding as the address-routing foundation, not just "the address selects the slave."

10. Practice Challenge

Reason from address decoding.

State the mechanism. Describe what the central decoder does, from HADDR to HSEL.
Centralized. Explain why decoding is centralized rather than per-slave, and what that gives.
Read the waveform. From Figure 2, explain why HSEL switches in the same cycle HADDR changes.
Disjoint + default. Explain what breaks if regions overlap, and what breaks if a gap has no default slave.
High bits. Explain why only the upper address bits select the slave and what the lower bits do.

11. Key Takeaways

Address decoding routes each transfer to one slave: a single central combinational decoder watches the shared HADDR, compares its upper bits against the system address map, and asserts exactly one slave's HSEL.
Only the selected slave (HSEL high) responds — all slaves see the same HADDR/HWRITE/HTRANS (broadcast), but the decoder's HSEL picks the one that responds; the rest ignore the transfer.
It's centralized — one decoder, so the address map is single-source-of-truth and slaves are address-agnostic/relocatable (a slave responds to HSEL, it doesn't decode HADDR).
It's combinational — HSEL is phase-aligned with HADDR (valid in the same address phase), so the slave samples both together; the decode delay is in the address-phase timing path.
The map must be disjoint and total — disjoint regions give one-hot HSEL (no multi-select/contention); a default slave covers gaps so every access has a target (no hang).
Decoding realizes the memory map in hardware and is the routing primitive that scales from one shared bus to a full interconnect fabric.

12. What Comes Next

You now understand address decoding — the central, combinational, one-hot selection of a slave from HADDR. The next chapters detail the mechanism and its surroundings:

HSEL Generation (next) — exactly how the decoder produces each slave's HSEL, and the per-slave HSEL timing.
The Default Slave — the slave that catches unmapped addresses and returns a defined (error) response.
The Address Map — defining an SoC address map and how it drives the decoder.

To revisit the AHB components this builds on, see Master, Slave, Decoder & Arbiter; for the shared-bus-vs-interconnect context, see Shared Bus vs Interconnect Thinking.