HTRANS

This chapter covers HTRANS, the transfer-type signal — and it is one of the most important signals in AHB, because it is what tells the bus whether this cycle's address phase is a real access at all, and how it relates to a burst. You have seen NONSEQ and SEQ informally in the pipelining and burst chapters; here we give all four HTRANS values their exact 2-bit encoding and precise meaning, and we settle the distinction that trips up the most people: IDLE versus BUSY. HTRANS is a critical interview signal precisely because that distinction reveals whether you truly understand burst behaviour.

1. What Is It?

HTRANS is a 2-bit address-phase signal, driven by the manager, that states the type of the current transfer. Its four values:

• 00 — IDLE: no transfer this cycle. The manager has nothing to do and is not in a burst. The selected subordinate must ignore it and respond OKAY.
• 01 — BUSY: the manager is inside a burst but cannot present the next beat yet — a mid-burst pause. The burst stays committed; the subordinate ignores the beat and responds OKAY.
• 10 — NONSEQ: a new, non-sequential access — the first beat of a burst, or a standalone single transfer. The address is unrelated to any previous beat.
• 11 — SEQ: a sequential continuation of a burst — the address follows the burst's pattern from the previous beat.

The essential framing: HTRANS classifies every address-phase cycle into "real transfer or not" and, if real, "start of a burst or continuation." NONSEQ and SEQ are the two real-transfer types (start vs continue); IDLE and BUSY are the two non-transfer types (idle vs mid-burst pause). Hold that 2×2 structure — real/not × start/continue and idle/pause — and HTRANS is fully captured.

2. Why Does It Exist?

HTRANS exists because the bus needs to know, every cycle, whether the address phase represents a real access and how it fits into a burst — and a single signal carrying that classification is what lets the pipeline, the subordinate, and the decoder behave correctly.

Consider what would go wrong without it. The address bus always has some value on it; without HTRANS, a subordinate could not tell a genuine access from a leftover address the manager simply has not changed. It needs an explicit "this is a real transfer" marker — and that is NONSEQ/SEQ versus IDLE/BUSY. So the first job of HTRANS is validity: it says whether the thing on the address bus this cycle is an access the subordinate should act on.

The second job is burst structure. A burst is a sequence of related beats, and the bus must distinguish the first beat (which establishes the burst — NONSEQ) from the continuation beats (which follow the pattern — SEQ). This lets a subordinate know "a new operation is starting" versus "the next beat of the operation you already know about," so it can prefetch and optimize. NONSEQ versus SEQ is how HTRANS expresses where you are in a burst.

The third job is handling mid-burst pauses. Sometimes a manager has started a burst but cannot supply the next beat in time — its source FIFO is momentarily empty, say. It needs a way to say "I'm still doing this burst, just not this cycle" without abandoning the burst. That is BUSY. It differs from IDLE precisely in that it keeps the burst alive: the subordinate knows more beats of the same burst are still coming. Without BUSY, a mid-burst stall would force the manager to either insert garbage or abandon and restart the burst — both worse.

So HTRANS exists to carry three pieces of information in one 2-bit signal: is this a real access, is it a burst start or continuation, and (if pausing) is the burst still alive. Those three are exactly what the rest of the bus needs to interpret every address-phase cycle correctly.

3. Mental Model

Model HTRANS as a delivery driver's status on each leg of a multi-stop route.

A driver doing a multi-stop delivery (a burst) reports a status at each moment:

• NONSEQ = "starting a new route" — the first stop of a fresh delivery run (or a one-off single delivery). A new destination unrelated to the last.
• SEQ = "next stop on the same route" — continuing the planned run to the next address in sequence.
• BUSY = "still on this route, but paused" — stuck at a light or loading, not yet at the next stop, but the route is not abandoned. The next stop is still coming.
• IDLE = "no route right now" — parked, nothing to deliver. Not in the middle of anything.

The dispatcher (subordinate) reads this status to know what to do: act on a NONSEQ/SEQ stop, prepare for the known next stop, wait through a BUSY without giving up on the route, and simply idle through an IDLE.

Watch all four types in one burst with a mid-burst pause:

The model's lesson: HTRANS narrates each cycle's role in the route. NONSEQ starts, SEQ continues, BUSY pauses-without-quitting, IDLE means no route. The BUSY cycle in the waveform is the one to study — the address holds at the next beat (A+8), the burst is not abandoned, and when the manager is ready it resumes with SEQ at that same address.

4. Real Hardware Perspective

In hardware, HTRANS is a manager output that every subordinate and the interconnect interpret to decide whether to act, and it interacts tightly with the pipeline and HREADY.

A subordinate uses HTRANS to qualify the access: on NONSEQ or SEQ it treats the address phase as a real access and will perform it in the data phase; on IDLE or BUSY it must not perform an access — it ignores the cycle and is required to respond OKAY (a non-transfer must not error). This "respond OKAY to IDLE/BUSY" rule matters: a subordinate that erred on an IDLE would break the protocol, since IDLE is normal and frequent.

The BUSY mechanics are the subtle hardware point. During BUSY, the manager remains committed to the burst: it holds the address of the next beat (the beat it will perform when it resumes), and HTRANS = BUSY tells the subordinate "ignore this cycle but expect the burst to continue." This lets a manager whose data source momentarily dries up (an empty FIFO feeding a write burst, say) pause cleanly without abandoning and re-arbitrating the burst. Note the difference from a wait state: a wait state is the subordinate holding HREADY low because it is not ready; BUSY is the manager signalling via HTRANS that it is not ready for the next beat. Two different "not ready"s, from two different sides.

Finally, HTRANS is an address-phase signal subject to the usual hold rule: it is driven in the address phase and, like the rest of the address-phase signals, the access it qualifies obeys the completion timing of HREADY. The transition pattern across a burst — NONSEQ, then SEQ for each continuation, with BUSY inserted for pauses, and IDLE between unrelated activity — is what a logic analyzer shows you, and reading it is how you reconstruct the burst structure from a capture.

5. System Architecture Perspective

At the system level, HTRANS is what makes burst-aware optimization possible and what keeps the bus's idle and pause behaviour clean — both matter for real performance and correctness.

Because HTRANS distinguishes NONSEQ (burst start) from SEQ (continuation), a subordinate — especially a memory controller — can use it to optimize. Seeing a NONSEQ, it knows a new operation is beginning and can use the accompanying HBURST/HSIZE to anticipate the whole burst; seeing SEQ, it knows the next beat of a known pattern is coming and can have it ready. This burst-awareness is how memories pipeline their internal operations and sustain bandwidth, and it is only possible because HTRANS explicitly marks the burst structure. Without that marking, every beat would look like an isolated access and the memory could not look ahead.

The IDLE behaviour is a system-level cleanliness property. Buses are not busy every cycle; between operations the manager drives IDLE, and the requirement that subordinates respond OKAY to IDLE (and ignore it) means the bus can sit between transfers without spurious accesses or errors. This is what lets a manager hold the bus (in a single-master AHB-Lite system, it always holds it) without doing anything — it just drives IDLE. IDLE is the bus's defined "resting" state, and it is frequent in real traffic.

BUSY connects to the realities of real data sources. Managers are often fed by FIFOs, and a FIFO can momentarily run dry mid-burst. BUSY lets the manager ride out that gap without losing the burst — important because abandoning and restarting a burst wastes the arbitration and burst-setup the system paid for, and would hurt the memory's optimization. So BUSY is the system's mechanism for tolerating bursty, imperfect data sources without sacrificing burst efficiency. In practice it lets a real DMA engine or bridge, whose data does not always arrive perfectly on time, still use efficient long bursts.

So HTRANS at the system level is the signal that makes bursts both expressible (NONSEQ/SEQ structure for memory optimization) and robust (BUSY for imperfect sources), while keeping the idle bus clean (IDLE). It is small but central to how a real AHB subsystem performs and behaves.

6. Engineering Tradeoffs

HTRANS embodies a few deliberate design choices worth naming.

• Explicit transfer-type vs implicit validity. AHB spends a 2-bit signal to mark transfer type explicitly, rather than inferring validity from other signals. The cost is two wires and the discipline to drive them correctly; the benefit is unambiguous, glitch-free classification of every cycle — essential on a pipelined bus where a stale address must be clearly distinguishable from a real one. Explicit is the right call.
• BUSY vs abandon-and-restart. Providing BUSY lets a manager pause mid-burst, at the cost of a little protocol complexity (a fourth transfer type and the rules around it). The alternative — forcing a manager to abandon a burst when its source stalls — would waste arbitration and burst setup and hurt memory optimization. BUSY trades a small protocol addition for robust, efficient bursts from imperfect sources.
• Separate IDLE and BUSY vs one "no transfer" code. AHB uses two distinct non-transfer codes rather than one, because the distinction (am I in a burst or not?) genuinely matters to the subordinate's burst tracking. The cost is one more encoding to understand; the benefit is that a subordinate always knows whether a burst is still in progress. The distinction earns its place.
• Manager-driven type vs negotiated. HTRANS is purely manager-driven — the manager declares the type, the subordinate reacts. This keeps the protocol simple (no negotiation) but means the manager bears responsibility for driving HTRANS correctly through a burst, including inserting BUSY rather than garbage when it stalls. Simplicity at the cost of manager-side discipline.

The through-line: HTRANS spends a small amount of signalling to make every cycle's role explicit and to make bursts robust. The four-way encoding, and especially the IDLE/BUSY distinction, are deliberate investments that pay off in unambiguous interpretation and efficient, fault-tolerant bursts — very much in keeping with AHB's "simple but capable" character.

7. Industry Example

Trace HTRANS through a DMA burst that hits a source stall — the canonical BUSY scenario.

A DMA engine (manager) is writing a buffer to memory as an incrementing burst, fed by an internal FIFO.

• Burst start (NONSEQ). The DMA wins the bus and drives HTRANS = NONSEQ at the first address, declaring the burst (with HBURST/HSIZE describing its shape and size). The memory subordinate sees NONSEQ and knows a new burst is beginning.
• Continuation (SEQ). On the next cycles the DMA drives HTRANS = SEQ with the address incrementing — beat after beat of the same burst. The memory, seeing SEQ, streams the beats efficiently, having anticipated the pattern.
• Source stall (BUSY). Midway, the DMA's feeding FIFO momentarily runs empty — it has no data for the next beat yet. Instead of abandoning the burst or writing garbage, the DMA drives HTRANS = BUSY, holding the address of the next beat. The memory sees BUSY, performs no access this cycle, responds OKAY, and keeps the burst context alive, knowing more SEQ beats are coming.
• Resume (SEQ). When the FIFO refills, the DMA returns to HTRANS = SEQ at the held address and continues the burst to completion. The burst survived the stall intact — no re-arbitration, no lost efficiency.
• Back to IDLE. When the whole transfer is done, the DMA drives HTRANS = IDLE; the bus rests, subordinates ignore the idle cycles and respond OKAY, and the DMA holds the bus quietly until its next operation.

Every cycle's behaviour here is governed by HTRANS: NONSEQ opened the burst, SEQ streamed it, BUSY rode out the FIFO stall without losing the burst, and IDLE returned the bus to rest. The BUSY handling is what let a real, imperfect data source (a FIFO that sometimes runs dry) still use an efficient long burst — exactly the robustness HTRANS's fourth code exists to provide.

8. Common Mistakes

9. Interview Insight

HTRANS is a high-frequency interview signal, and the IDLE-versus-BUSY distinction is almost always the real question.

The answer that lands gives the four encodings and nails the distinctions: "HTRANS is 2 bits. NONSEQ is the first beat of a burst or a single transfer; SEQ is a burst continuation whose address follows the pattern. IDLE means no transfer and not in a burst; BUSY means the manager is paused mid-burst but keeps the burst alive. A subordinate performs no access on IDLE or BUSY and responds OKAY. And crucially, BUSY is the manager not being ready, which is different from a wait state, where the subordinate isn't ready." The BUSY-versus-wait-state and BUSY-keeps-the-burst points are the senior signals.

10. Practice Challenge

Reason from the 2×2 structure and the IDLE/BUSY distinction.

1. Encode the four. Give the 2-bit encoding and one-line meaning of each HTRANS value.
2. Place the cycles. For "bus resting," "first beat of a DMA burst," "third beat of that burst," and "manager's FIFO ran dry mid-burst," name the HTRANS value.
3. Read the waveform. In Figure 2, identify the NONSEQ, SEQ, and BUSY cycles and explain what the address does during BUSY.
4. Distinguish the pauses. In two sentences, contrast BUSY with a wait state, naming which side of the bus drives each.
5. Diagnose the bug. A subordinate shows phantom accesses when the bus is idle. Name the likely HTRANS-handling error and the fix.

11. Key Takeaways

• HTRANS is a 2-bit transfer-type signal: IDLE (00), BUSY (01), NONSEQ (10), SEQ (11). NONSEQ/SEQ are real transfers; IDLE/BUSY are non-transfers.
• NONSEQ starts a burst (or is a single transfer); SEQ continues a burst with the address following the pattern. The first beat is NONSEQ, not SEQ.
• IDLE means no transfer and not in a burst; BUSY means a mid-burst pause that keeps the burst alive — the manager holds the next beat's address and resumes with SEQ.
• BUSY (manager not ready) is not a wait state (subordinate not ready) — opposite sides of the bus. This is the most-tested HTRANS distinction.
• On IDLE or BUSY a subordinate performs no access and must respond OKAY — mishandling IDLE causes phantom accesses and spurious errors, since IDLE is frequent.
• HTRANS makes bursts both expressible and robust — NONSEQ/SEQ structure lets memories optimize, and BUSY lets imperfect data sources sustain efficient bursts.

12. What Comes Next

You now know how each cycle is classified. The next signals quantify the access:

• 3.4 — HSIZE (coming next) — the transfer-size encoding (byte, halfword, word, and wider) that, with HADDR, fixes alignment and byte lanes.
• 3.5 — HBURST (coming soon) — the burst-type encoding (SINGLE, INCR, WRAP and their lengths) whose structure HTRANS's NONSEQ/SEQ expresses cycle by cycle.

To revisit how HTRANS drives burst and pipeline behaviour, see Single Transfer vs Burst Transfer and Pipelined Operation; for the address-phase context, see The Address / Control Phase and HADDR & HWRITE. For the broader protocol map, see the AMBA family overview.