SEQ Transfers

This chapter covers SEQ, the transfer type that continues a burst — the partner to NONSEQ (4.4). Every beat of a burst after the first is SEQ, and SEQ carries two important rules: its address must follow the burst pattern, and the control signals stay constant across the whole burst. SEQ is what makes a burst a single, coherent operation rather than a string of unrelated accesses, and the constraints on it are exactly what let the subordinate stream a burst efficiently. We cover SEQ's meaning, the pattern-address rule, what stays constant, and why SEQ can never start a burst. This builds on NONSEQ (4.4), the overview (4.1), and the burst chapter (2.6).

1. What Is It?

SEQ (HTRANS = 11) is a real transfer that continues a burst. Every beat of a burst after the opening NONSEQ beat is SEQ. Its two defining rules:

• The address must follow the burst pattern — the previous beat's address plus the beat size for an incrementing burst, or the wrapped address for a wrapping burst. It is not arbitrary (the contrast with NONSEQ).
• The control signals stay constant — HWRITE (direction), HSIZE (beat size), HBURST (burst type), and HPROT (attributes) are the same for every beat of the burst; only the address changes.

And one structural rule: SEQ only appears after a NONSEQ has opened the burst — SEQ can never start a burst.

The essence: SEQ is the master saying "continuing the burst, at the next pattern address." Where NONSEQ has address freedom (it starts anywhere), SEQ is constrained — its address must match the burst, and the burst's shape (direction, size, type) is fixed. These constraints are not limitations to work around; they are exactly what makes a burst a predictable, optimizable sequence the subordinate can stream.

2. Why Does It Exist?

SEQ exists because a burst's continuation beats are predictable by construction, and marking them as such (with a constrained address and frozen control) is what lets the subordinate stream the burst efficiently.

Recall why bursts exist (chapter 2.6): they let a master declare a sequence of related beats up front so the subordinate can anticipate and optimize. For that to work, the continuation beats must actually be predictable — their addresses must follow the declared pattern, and the access shape (direction, size) must not change mid-burst. SEQ is the transfer type that enforces this predictability: by definition, a SEQ beat's address follows the pattern and its control matches the burst. So SEQ exists to make the continuation beats of a burst the predictable, pattern-following accesses that burst optimization requires. If continuation beats could have arbitrary addresses or changing control, they would not be a burst — they would be unrelated accesses, and the subordinate could not anticipate them.

The constant-control rule exists because a burst is one operation. A 4-beat word write burst is "write four words" — a single coherent operation with a fixed direction (write), a fixed size (word), and a fixed pattern (incrementing). It would make no sense for beat 2 to suddenly become a read, or a halfword, or part of a different burst type. So the control signals are frozen across the burst: the operation's shape is set at the NONSEQ that opens it, and the SEQ beats carry it out unchanged. This is why HWRITE, HSIZE, HBURST, and HPROT are constant — the burst is one operation, and its shape is fixed.

The SEQ-only-after-NONSEQ rule exists because a continuation must have something to continue. SEQ means "continue the burst," which presupposes a burst is in progress — opened by a NONSEQ. A SEQ with no preceding NONSEQ would be claiming to continue a burst that never started, which is meaningless (and a protocol error). So the structural ordering — NONSEQ opens, SEQ continues — is intrinsic to what the types mean. This ordering is the grammar from the overview chapter: every burst is NONSEQ then SEQ…, never SEQ first.

So SEQ exists to mark the predictable, pattern-following, fixed-shape continuation beats that make a burst an optimizable operation — and its rules (pattern address, constant control, after-NONSEQ-only) are precisely what enforce that predictability.

3. Mental Model

Model SEQ as the verses of a song after the first line sets the tune.

The first line of a song (NONSEQ) establishes the key, the tempo, and the melody — it can be anything. After that, the verses (SEQ) follow the established pattern: same key, same tempo, with the melody progressing predictably. You cannot suddenly switch keys or tempos mid-verse (control is frozen), and the melody moves in the expected way (the address follows the pattern). And you cannot sing a verse before the opening line has set the tune (SEQ only after NONSEQ). The song is one coherent piece — the opening sets its shape, the verses carry it out.

Watch a burst's SEQ beats:

The model's lesson: SEQ beats are the verses that follow the opening line's tune — pattern-following address, frozen control. In the waveform, HADDR climbs by the pattern while HWRITE and HSIZE never change: that constancy is the visual signature of a single coherent burst, and the NONSEQ-then-SEQ sequence is its grammar.

4. Real Hardware Perspective

In hardware, SEQ tells the subordinate to continue the established burst, and the master's address generation plus the constant-control rule are what make this work.

When a subordinate sees a committed SEQ (qualified by HSEL and HREADY — chapter 4.7), it continues the burst it established on the NONSEQ: it does not re-establish a fresh access or re-decode a new burst context; it advances the existing one. The subordinate, having anticipated the pattern from the NONSEQ's HBURST/HSIZE, already knows where the SEQ beats are going and can have them ready (prefetched data, an open row). So SEQ is the cue to advance the burst, leveraging the setup done at the NONSEQ — which is exactly the source of burst efficiency. The master, for its part, generates each SEQ beat's address by the pattern rule (a simple counter incrementing by the beat size, or wrapping), and holds the control signals constant.

The constant-control rule is a hardware obligation on the master: across the burst, it must drive the same HWRITE, HSIZE, HBURST, and HPROT for every beat. In hardware this is natural — the master registers the burst's parameters at the start and holds them — but violating it (changing a control signal mid-burst) breaks the subordinate's assumption that the burst's shape is fixed, corrupting the burst. So a correct master freezes the control for the burst's duration; the address generator is the only thing that advances.

The pattern-address rule is the other master obligation: each SEQ beat's address must follow the burst pattern. For an incrementing burst, that is previous + beat size; for a wrapping burst, the wrapped address. The subordinate relies on this — it has prefetched or prepared for the pattern addresses, so a SEQ with an off-pattern address would defeat its optimization and, more seriously, would be a protocol violation (the access is not where the burst said it would be). The master's address generator must implement the pattern correctly, including the wrap behaviour for WRAP bursts (chapter 3.5) and respecting the 1 KB boundary rule (a burst must not cross a 1 KB boundary, so the master breaks bursts at boundaries rather than letting a SEQ cross one).

A hardware consequence of "SEQ only after NONSEQ": a subordinate should not see a SEQ as the first beat of activity. If it did (a SEQ with no preceding NONSEQ in the burst), that is a protocol error indicating a buggy master — the subordinate has no burst context to continue. Protocol checkers verify the NONSEQ-then-SEQ ordering precisely because a stray SEQ indicates a master bug.

5. System Architecture Perspective

At the system level, SEQ is where burst efficiency is realized, and its constraints are what the memory subsystem depends on to sustain bandwidth.

The memory subsystem's burst optimization (anticipate the pattern, prefetch, manage rows) pays off during the SEQ beats. The NONSEQ establishes the burst; the SEQ beats are where the memory streams data from its prepared state, beat after beat, at high bandwidth. So SEQ is the system-level workhorse of bulk data movement — the cycles where a burst actually delivers its throughput. A system's sustained bandwidth on bursts is essentially the rate at which SEQ beats complete, which is why keeping the SEQ stream flowing (no unnecessary BUSY pauses, no wait states) is the performance goal for bulk transfers.

The constant-control and pattern-address rules are what make this system-level optimization possible and correct. Because the control is frozen and the addresses follow the pattern, the memory can prepare for the entire burst at the NONSEQ and trust the SEQ beats to match — no surprises mid-burst. If a master violated these rules (changing control mid-burst, or off-pattern SEQ addresses), the memory's preparation would be wrong, defeating the optimization and likely corrupting the access. So the discipline on SEQ is not bureaucracy — it is the contract that lets the memory subsystem optimize bursts. The system's burst performance rests on masters honouring the SEQ rules.

The NONSEQ-vs-SEQ ratio is a system-level performance indicator. A master doing efficient bulk transfers shows few NONSEQ and many SEQ (long bursts — one start, many continuations). A master doing inefficient small accesses shows many NONSEQ and few SEQ (single transfers or short bursts — much starting, little continuing). So reading the NONSEQ:SEQ ratio reveals whether a master is using the bus efficiently. The system optimization goal is to maximize SEQ beats per NONSEQ — longer bursts amortize the start over more continuations, which is the bandwidth win. This connects SEQ directly to the system's throughput characteristics.

So at the system level, SEQ is where bursts deliver bandwidth, its rules are the contract enabling memory optimization, and its ratio to NONSEQ indicates how efficiently a master uses the bus.

6. Engineering Tradeoffs

SEQ's rules reflect the discipline that makes bursts work.

• Constrained address (SEQ) vs free address (NONSEQ). SEQ's pattern-following address is a constraint, but it is exactly what lets the subordinate prefetch and stream — the constraint buys efficiency. The free address of NONSEQ is for starting; the constrained address of SEQ is for efficient continuation. The two together give both flexibility (start anywhere) and efficiency (continue predictably).
• Frozen control vs mid-burst flexibility. Freezing control across a burst means you cannot change direction or size mid-burst — a flexibility cost. But it makes the burst one coherent, predictable operation the subordinate can optimize. If you need a different shape, you start a new burst (NONSEQ). The trade is mid-burst flexibility for burst coherence and optimizability — clearly worth it.
• Long bursts (more SEQ) vs latency. Maximizing SEQ beats per NONSEQ (longer bursts) amortizes the start and sustains bandwidth, but longer bursts hold the bus longer (the arbitration/latency tradeoff from chapter 2.6) and are bounded by the 1 KB rule. So there is an optimal burst length balancing efficiency (more SEQ) against others' latency. SEQ is the efficiency side of that balance.
• Strict SEQ rules vs lenient. Enforcing the pattern-address and constant-control rules strictly (a violation is a protocol error) keeps bursts unambiguous and optimizable, at the cost of requiring masters to implement them correctly. A lenient scheme allowing off-pattern SEQ would defeat optimization and breed bugs. Strictness is the right choice — the rules are what make SEQ meaningful.

The throughline: SEQ trades address and control freedom for predictability — the pattern-following address and frozen control are constraints that enable burst efficiency rather than limit it. The system maximizes SEQ-per-NONSEQ (longer bursts) for bandwidth, within the latency and 1 KB-boundary bounds. SEQ is the disciplined continuation that makes bursts the efficient bulk-transfer mechanism they are.

7. Industry Example

Trace SEQ through a DMA's incrementing write burst.

A DMA engine writes a block to memory as a 4-beat incrementing word burst.

• NONSEQ opens the burst. The DMA drives NONSEQ at the starting address A, with HWRITE = write, HSIZE = word, HBURST = INCR4. The memory, seeing the NONSEQ with these parameters, establishes its burst context: it knows four word writes are coming at A, A+4, A+8, A+12, and prepares (opens the row, readies to accept the data).
• SEQ beats continue the burst. The DMA drives SEQ for beats 1–3, at addresses A+4, A+8, A+12 — each following the incrementing pattern. Critically, HWRITE stays write, HSIZE stays word, HBURST stays INCR4 for every beat — the control is frozen. The memory, having prepared, streams the writes from its ready state at high bandwidth. This is where the burst delivers its throughput.
• The efficiency, concretely. The decode and burst setup happened once, at the NONSEQ. The three SEQ beats leveraged that setup — no re-decode, no re-setup, just continuation at the pattern addresses. Compared to four single transfers (four NONSEQ, four setups), the burst paid the setup once and amortized it across the SEQ beats. The SEQ beats are the efficient part.
• A control-change bug (if present). Suppose the DMA were buggy and drove beat 2 as a halfword (HSIZE changed mid-burst). The memory, prepared for word writes, would see a beat claiming halfword — a control-change violation that corrupts the access and breaks the burst's coherence. A correct DMA freezes HSIZE (and all control) across the burst.
• The waveform signature. On a capture, this burst shows NONSEQ then SEQ, SEQ, SEQ, with HADDR climbing A, A+4, A+8, A+12 and HWRITE/HSIZE/HBURST flat. The flat control and climbing address are the visual signature of a correct burst; any control wiggle or off-pattern address jump on a SEQ beat would flag a bug.

The burst shows SEQ's role: the continuation beats that, with frozen control and pattern addresses, let the memory stream efficiently — amortizing the NONSEQ's setup across them. SEQ is where bursts pay off.

8. Common Mistakes

9. Interview Insight

SEQ questions test the pattern-address and constant-control rules, and the after-NONSEQ ordering.

The answer that lands gives SEQ's rules: "SEQ is a continuation beat of a burst — every beat after the first NONSEQ. Two rules: its address must follow the burst pattern (previous plus the beat size, or wrapped), and the control signals — HWRITE, HSIZE, HBURST, HPROT — stay constant across the whole burst; only the address changes. And SEQ only ever follows a NONSEQ; it can't start a burst. These constraints are what let the subordinate prefetch and stream the burst efficiently — SEQ leverages the setup the NONSEQ did." The pattern-address rule, the constant-control rule, and the after-NONSEQ ordering are the senior signals.

10. Practice Challenge

Reason from the pattern-address and constant-control rules.

1. Define SEQ. State what SEQ marks and its two rules (pattern address, constant control), plus the after-NONSEQ ordering.
2. What changes. For a 4-beat incrementing word write burst, list which signals change across the beats and which stay constant.
3. Read the waveform. From Figure 2, confirm the address pattern and that the control is frozen.
4. Explain the efficiency. In three sentences, explain how SEQ leveraging the NONSEQ's setup makes a burst efficient.
5. Diagnose corruption. Burst data corrupts tracking the burst shape. Explain how a mid-burst control change or off-pattern SEQ address causes it.

11. Key Takeaways

• SEQ (11) is a continuation beat of a burst — every beat after the opening NONSEQ.
• A SEQ's address must follow the burst pattern (previous + beat size, or wrapped) — not arbitrary, which is the contrast with NONSEQ.
• Control signals are frozen across a burst — HWRITE, HSIZE, HBURST, HPROT are constant; only the address and the NONSEQ-to-SEQ transition change.
• SEQ only follows a NONSEQ — it can never start a burst; a stray SEQ is a protocol error.
• SEQ's constraints enable burst efficiency — they let the subordinate prefetch and stream from the setup done at the NONSEQ; SEQ leverages that setup rather than re-establishing it.
• The classic bugs are off-pattern SEQ addresses and mid-burst control changes — both corrupt the burst and are protocol violations. Across a burst: follow the pattern, freeze the control.

12. What Comes Next

You now know both real-transfer types and the full transfer-type set. The next chapter ties them together by showing how HTRANS controls whether work actually happens each cycle:

• 4.6 — How HTRANS Controls Bus Activity (coming next) — connecting the transfer types to whether the bus and subordinate do real work each cycle.
• 4.7 — Valid Transfer Identification (coming soon) — the rule for recognizing a committed transfer (HTRANS + HSEL + HREADY).

To revisit the type that opens the burst SEQ continues, see NONSEQ Transfers; for the burst structure and the wrap/increment patterns SEQ follows, see Single Transfer vs Burst Transfer and HBURST. For the broader protocol map, see the AMBA family overview.