HSEL Generation

Chapter 11.1 established that a central decoder asserts one slave's HSEL. This chapter details how that HSEL is generated and how the slave uses it. The decoder runs one address comparator per slave region: each checks whether HADDR's upper bits fall in its region, outputting one bit. Because the regions are disjoint, at most one comparator fires — so HSEL is one-hot (exactly one line high). Each slave gets its own dedicated HSEL line (point-to-point), separate from the broadcast HADDR/control. HSEL is combinational on HADDR, so it's valid in the address phase; the slave samples HSEL together with HADDR, HWRITE, HTRANS at the clock edge, qualifies it with HTRANS (respond only to a real transfer), and then responds in the data phase. This chapter covers the generation logic, the one-hot property, the address-phase timing, and the HTRANS qualification — the precise mechanics behind slave selection.

1. What Is It?

HSEL generation is how the decoder produces each slave's select line from HADDR, and how the slave consumes it. The mechanism:

• One comparator per region. For each slave region, the decoder compares HADDR's upper bits against that region's address tag.
• One-hot output. Disjoint regions mean at most one comparator matches → exactly one HSEL is high (one-hot).
• Per-slave line. Each slave has its own HSEL input, driven point-to-point from the decoder.
• Address-phase timing. HSEL is combinational on HADDR, so it's valid in the address phase; the slave samples it with HADDR/control and responds the next (data) phase.

So HSEL generation is the comparator bank that turns an address into a one-hot select, and the per-slave wiring that delivers each select. The slave then uses HSEL by sampling it in the address phase (with HADDR/control), qualifying it with HTRANS, and responding in the data phase. So this is the full life of HSEL: generated combinationally from HADDR (one-hot), delivered per-slave, sampled in the address phase, and acted on in the data phase. HSEL is the bit that says "you're the one" — generated by the decoder, consumed by the slave.

2. Why Does It Exist?

HSEL generation exists in this form — one-hot, per-slave, combinational, HTRANS-qualified — because each property solves a specific selection problem: one-hot prevents multi-select, per-slave lines keep slaves simple, combinational keeps the select phase-aligned, and HTRANS-qualification prevents responding to non-transfers.

The one-hot property exists to ensure exactly one responder. The whole point of selection is to pick one slave. If the decode could assert two HSELs (multi-select), two slaves would respond → contention. If it could assert zero (for a mapped address), no slave responds → hang. So the decode is designed to be one-hot: disjoint regions guarantee at most one match, and the default slave guarantees at least one (covering gaps) — so exactly one HSEL is high for every address. So one-hot generation exists to guarantee a single, well-defined responder. So the comparator structure (disjoint regions + default) exists to produce one-hot HSEL.

The per-slave dedicated line exists to keep slaves simple and decoupled: each slave needs only a single HSEL input to know "am I selected?" — it doesn't need to see other slaves' selects or decode HADDR. So the decoder fans out one HSEL per slave, point-to-point. This keeps each slave a self-contained block that just watches its own HSEL. So per-slave HSEL exists to decouple slaves from the decode and from each other. So the decoder's output is a bundle of per-slave selects, one each.

The combinational generation exists for phase alignment (as in 11.1): HSEL must be valid in the address phase, alongside HADDR, so the slave samples them together. A registered decode would delay HSEL by a cycle. So generation is combinational to keep HSEL address-phase-aligned. So the decode logic is combinational.

The HTRANS qualification exists because HSEL alone isn't enough — a slave can be selected (HSEL high) even when the master isn't doing a real transfer. HSEL is decoded from HADDR, which is driven even during IDLE/BUSY transfers (HTRANS = IDLE or BUSY). So a slave with HSEL high during an IDLE transfer should not respond (there's no real transfer to respond to). So the slave qualifies HSEL with HTRANS: it responds only when HSEL is high and HTRANS indicates a real transfer (NONSEQ or SEQ). This prevents the slave from acting on a non-transfer. So HTRANS-qualification exists to ensure the slave responds only to real transfers, not to IDLE/BUSY cycles where HSEL happens to be high. So HSEL generation and use exist in this form — one-hot (single responder), per-slave (decoupled slaves), combinational (phase-aligned), HTRANS-qualified (real transfers only) — each property solving a selection correctness problem.

3. Mental Model

Model HSEL generation as a row of name-tag scanners at an event entrance — each scanner is set to recognize one guest's badge ID; when a badge (the address) is presented, exactly one scanner lights up (one-hot), and that guest's turnstile opens — but only if the entrance is actually "open for entry" (a real transfer), not during a maintenance pause (IDLE) where badges might still be waved.

At an event entrance, there's a row of scanners (comparators), each set to recognize one guest's badge ID (one region tag). When a badge is presented (HADDR), exactly one scanner lights up — the one whose ID matches (one-hot HSEL) — and that guest's turnstile (slave) is signaled to open. Each turnstile watches only its own scanner's light (its own HSEL line), not the others'. But there's a catch: the turnstile opens only if the entrance is in "open for entry" mode (a real transfer, HTRANS = NONSEQ/SEQ) — during a maintenance pause (IDLE/BUSY), a badge might still be waved near a scanner (HSEL high), but the turnstile should not open (no real entry is happening). So the turnstile checks both its scanner light and the entrance mode. One scanner lights per badge, each turnstile watches its own light, and the turnstile opens only when the entrance is genuinely admitting — clean, single, qualified selection.

This captures HSEL generation: the scanners = the per-region comparators; the badge ID = HADDR's upper bits; exactly one scanner lighting = one-hot HSEL; each turnstile watching its own light = per-slave HSEL line; the entrance mode (open vs maintenance) = HTRANS (real transfer vs IDLE/BUSY); the turnstile opening only when admitting = the slave responding only when HSEL high and HTRANS is a real transfer. One light per badge, watched per-turnstile, gated by the entrance mode.

Watch HSEL generation and qualification cycle by cycle:

The model's lesson: one scanner lights per badge, each turnstile watches its own — but only opens when the entrance is truly admitting. In the waveform, HSEL_0 is high in cycles 0–2, but the slave responds only when HTRANS is also a real transfer (cycles 0, 2) — not during the IDLE (cycle 1).

4. Real Hardware Perspective

In hardware, the decoder is the comparator bank producing one-hot HSEL, and each slave's front-end qualifies HSEL with HTRANS and registers the qualified select into its data-phase response logic.

The decoder side is the comparator bank from 11.1: one comparison per region against HADDR's upper bits, structurally guaranteeing one-hot (disjoint regions). The HSEL outputs are registered nowhere in the decoder — they're combinational — and fan out point-to-point to the slaves. So the decoder's HSEL generation is the combinational comparator bank, one output per slave.

The slave side is where HSEL is consumed: the slave's front-end samples HSEL, HADDR, HWRITE, HTRANS, HSIZE at the clock edge ending the address phase. It computes a qualified select: select = HSEL && (HTRANS == NONSEQ || HTRANS == SEQ) — true only when this slave is addressed and a real transfer is happening. This qualified select is what the slave acts on. The slave typically registers this qualified select (and the relevant address-phase info) into its data-phase logic, so that in the data phase it drives the right response (HREADY, HRESP, read data) for the transfer that was addressed to it. So HSEL flows: combinational from the decoder (address phase) → sampled and qualified by the slave (address phase) → registered into the slave's data-phase response (data phase). So in hardware, the decoder generates HSEL combinationally and the slave qualifies-and-registers it to drive the aligned data-phase response.

The timing-path note: because HSEL is combinational on HADDR, the path HADDR → decoder comparators → HSEL → slave's address-phase sampling must settle within the address phase. In a large interconnect this can be a critical path. The slave's registering of the qualified select aligns the response to the data phase. So the hardware splits HSEL into a combinational generate-and-sample (address phase) and a registered respond (data phase) — matching the AHB two-phase pipeline. So in hardware, HSEL generation is combinational, its consumption is qualified-and-registered, and the whole thing is timed to the address/data phase split.

5. System Architecture Perspective

At the system level, HSEL generation is where the address map's structure (disjoint regions, a default) becomes the one-hot guarantee, and the HTRANS qualification is part of the slave-protocol contract that keeps the bus robust.

The one-hot guarantee as a system invariant: the system relies on exactly one slave responding to each transfer. HSEL generation enforces this structurally: disjoint regions (no two comparators match) + a default slave (always at least one match) = one-hot HSEL = exactly one responder. So the address map's structure is the one-hot guarantee — a well-formed map (disjoint + default) produces correct selection by construction. So at the system level, HSEL generation ties the map's well-formedness to the selection invariant. This is why address-map verification (no overlap, default coverage) is a system-level concern: it's what makes HSEL one-hot.

The slave-contract view: the HTRANS qualification is part of every AHB slave's protocol contract — a correct slave responds only when selected and a real transfer is happening. This is a system-level robustness property: it means slaves don't spuriously respond during IDLE/BUSY cycles (which occur naturally — a master inserting IDLEs between transactions, or BUSY mid-burst). So the qualification keeps the bus robust against the natural IDLE/BUSY traffic. A slave that ignored HTRANS (responded on HSEL alone) would misbehave during IDLEs. So the system relies on every slave qualifying HSEL with HTRANS. So at the system level, HSEL generation (one-hot, from a well-formed map) and HSEL consumption (HTRANS-qualified, per the slave contract) together make slave selection correct and robust — the map structure guarantees one responder, and the slave contract ensures that responder acts only on real transfers. This is the selection layer of the interconnect: it scales (more slaves = more comparators/HSELs), it's verified (map well-formedness + slave-contract compliance), and it's the foundation on which the data-routing (read-data muxing back to the master) is built. So HSEL generation is the precise realization of the selection mechanism that 11.1 introduced — the comparator-to-one-hot generation plus the qualified-and-registered consumption.

6. Engineering Tradeoffs

HSEL generation embodies the one-hot-select design.

• One-hot (structural) vs encoded select. One-hot HSEL (one line per slave) is simple for the slave (check one bit) and naturally per-slave, at the cost of one wire per slave. An encoded select (log2 lines) saves wires but needs a decoder at each slave. AHB uses one-hot per-slave HSEL.
• Combinational generate vs registered. Combinational HSEL is address-phase-aligned (sampled with HADDR) at the cost of being in the address-phase timing path. Registering would relax timing but misalign. AHB generates combinationally; slaves register the qualified select for the data phase.
• HTRANS-qualified vs HSEL-only response. Qualifying with HTRANS makes the slave robust to IDLE/BUSY (responds only to real transfers) at the cost of a little more slave logic. Responding on HSEL alone is simpler but wrong (spurious response during IDLE). Qualification is required for correctness.
• Disjoint-map structure vs runtime check. Relying on a disjoint map (verified at design time) for one-hot is free at runtime, at the cost of design-time verification. A runtime multi-select check would catch map bugs but cost logic. AHB relies on a well-formed map.

The throughline: HSEL generation runs one comparator per region on HADDR's upper bits, producing one-hot HSEL (disjoint regions → one match; default → at least one); each slave gets a dedicated line; HSEL is combinational (address-phase-valid); and the slave qualifies it with HTRANS (respond only to a real transfer) and registers the qualified select for its data-phase response. It's the precise realization of slave selection: one-hot for a single responder, per-slave for decoupled slaves, combinational for phase alignment, HTRANS-qualified for robustness.

7. Industry Example

Trace HSEL through a slave's front-end.

A peripheral slave (a UART) sits in a system; the decoder drives its HSEL_UART.

• A real write to the UART. The master drives HADDR in the UART's region with HTRANS = NONSEQ (a real transfer) and HWRITE = 1. The decoder asserts HSEL_UART (one-hot — only the UART). The UART's front-end samples HSEL_UART = 1, HTRANS = NONSEQ → qualified select = 1. It registers this, and in the data phase accepts the write data, driving HREADY high (and HRESP = OKAY). So the write is performed.
• An IDLE cycle with HADDR still in the UART's region. Between transactions, the master drives HTRANS = IDLE but HADDR happens to still point into the UART's region. So HSEL_UART = 1 (decoded from HADDR) — but HTRANS = IDLE. The UART's qualified select = HSEL_UART && (HTRANS real) = 1 && 0 = 0. So the UART does not respond — no spurious access. (It still drives HREADY high with HRESP = OKAY as a selected-but-idle slave should, but performs no read/write side effect.) So the IDLE is correctly ignored.
• A BUSY mid-burst. During a burst to the UART, the master inserts HTRANS = BUSY (it needs a cycle). HSEL_UART = 1, but HTRANS = BUSY → qualified select = 0 for the data action. The UART holds (zero-wait OKAY, no side effect) until the burst resumes (SEQ). So the BUSY is correctly handled.
• A real read to the UART. HADDR in the UART's region, HTRANS = NONSEQ, HWRITE = 0. HSEL_UART = 1, qualified = 1. The UART drives the read data in the data phase. So the read is performed.

The example shows HSEL's full life: generated one-hot by the decoder, sampled by the slave with HADDR/control, qualified with HTRANS so the slave acts only on real transfers (NONSEQ/SEQ) and not on IDLE/BUSY, and registered to drive the data-phase response. The HTRANS qualification is what makes the slave robust to the natural IDLE/BUSY traffic on the bus.

8. Common Mistakes

9. Interview Insight

HSEL generation is a precise interview topic — the one-hot generation, the address-phase timing, and especially the HTRANS qualification are the signals.

The answer that lands covers generation, timing, and qualification: "The decoder generates HSEL with one comparator per slave region — each checks whether HADDR's upper bits fall in its region. Because the regions are disjoint, at most one comparator fires, so HSEL is one-hot — exactly one slave's select is high (the default slave covers unmapped addresses, so it's never zero). Each slave gets its own dedicated HSEL line. HSEL is combinational on HADDR, so it's valid in the address phase — the slave samples HSEL together with HADDR, HWRITE, HTRANS at the clock edge ending the address phase. Crucially, the slave qualifies HSEL with HTRANS: it responds only when HSEL is high and HTRANS is a real transfer (NONSEQ or SEQ) — not during IDLE or BUSY, where HSEL might be high but there's no real transfer. This prevents spurious reads or writes. The slave registers this qualified select into its data-phase logic, so it drives the right response (HREADY, HRESP, read data) in the data phase for the transfer addressed to it." The one-hot generation, the address-phase timing, and the HTRANS qualification are the senior signals — especially catching the IDLE/BUSY case.

10. Practice Challenge

Reason from HSEL generation.

1. Generation. Describe how the decoder produces one-hot HSEL from HADDR.
2. One-hot. Explain why HSEL is one-hot — what guarantees at most one, and what guarantees at least one.
3. Read the waveform. From Figure 2, explain why the slave responds in cycles 0 and 2 but not cycle 1, even though HSEL is high in all three.
4. Qualification. Explain why a slave must qualify HSEL with HTRANS and what bug appears if it doesn't.
5. Registering. Explain where the slave registers the qualified select and why (the pipeline).

11. Key Takeaways

• The decoder generates HSEL with one comparator per region (HADDR's upper bits vs the region tag); disjoint regions make at most one match, the default slave makes at least one → one-hot HSEL (exactly one high).
• Each slave has its own dedicated HSEL line (point-to-point) — so a slave checks one bit to know it's selected; it doesn't decode HADDR or see other selects (decoupled, relocatable).
• HSEL is combinational on HADDR — valid in the address phase, sampled by the slave together with HADDR/HWRITE/HTRANS at the clock edge.
• The slave must qualify HSEL with HTRANS — respond only when HSEL is high and HTRANS is a real transfer (NONSEQ/SEQ), never on HSEL alone (which would cause spurious reads/writes during IDLE/BUSY).
• The slave registers the qualified select into its data-phase logic, so its response (HREADY, HRESP, read data) lands in the data phase, matching the AHB pipeline.
• A slave that ignores HTRANS is a classic bug — it passes simple tests but misbehaves under realistic IDLE/BUSY traffic.

12. What Comes Next

You now understand HSEL generation — the one-hot comparator bank, the address-phase timing, and the HTRANS qualification. The next chapters complete the selection picture:

• The Default Slave (next) — the slave the decoder selects for unmapped addresses, and the defined (error) response it returns.
• The Address Map — defining an SoC address map (disjoint regions, alignment) that drives the decoder's comparators.
• Illegal Address Behavior — what happens on access to an unmapped region.

To revisit the decode overview, see Address Decoding; for HTRANS itself, see HTRANS & Bus Control.