Structured paths through the curriculum.
Programs organize existing tutorials into ordered, module-by-module learning paths. The lessons are the same reading-first tutorials — a program simply gives them a sequence, prerequisites, and a destination.
SystemVerilog Fundamentals
The SystemVerilog language core — before verification.
A structured path through the SystemVerilog language itself: data types, arrays, procedural code, tasks and functions, hierarchy, packages, and interfaces. It organizes existing tutorials into one ordered sequence so you can move from Verilog to a solid SystemVerilog foundation before stepping into OOP-based verification.
SystemVerilog for Verification
OOP, constrained random, coverage, and assertions.
The verification half of SystemVerilog: object-oriented testbench programming, constrained-random stimulus, functional coverage, assertions, and the concurrency that ties a testbench together. It continues directly from SystemVerilog Fundamentals into the language features verification engineers use every day — the groundwork for UVM.
UVM Fundamentals
Architecture, base classes, phasing, factory, and config_db.
The conceptual and structural foundation of the Universal Verification Methodology: why it exists, its testbench architecture, the uvm_object / uvm_component base classes, the phasing schedule, the factory, and top-down configuration with the config_db. It sequences existing UVM tutorials into one path that prepares you to read and build real UVM environments.