The Address / Control Phase

This is where AHB becomes concrete. Until now we have stayed above the wires; from here the transfer is described in signals. Every AHB access has two phases, and this chapter is the first of them: the address phase (often called the address/control phase), in which the manager announces everything about the access it wants to perform — except the data itself. We will meet the address-phase signals by name, see how the decoder and the selected subordinate use them, and understand precisely why this phase must come before the data phase. We will keep the bit-level encodings light — the full encoding of each signal is the subject of Module 3 — and focus on the role each plays in the address phase and how they fit the two-phase model you already hold.

1. What Is It?

The address phase is the first clock cycle of an AHB transfer, during which the manager drives a group of control signals that completely describe the access — what address, which direction, what kind of transfer, what size, what burst shape — while no data has yet moved. It is the "announcement" half of the transfer; the data phase that follows is the "execution" half.

The signals the manager drives in the address phase are:

• HADDR — the address of the access. This is what the decoder reads to select a subordinate.
• HWRITE — the direction: a write (manager → subordinate) or a read (subordinate → manager).
• HTRANS — the transfer type: whether this is a real access and whether it is part of a burst (the values IDLE, BUSY, NONSEQ, SEQ — detailed in Module 3).
• HSIZE — the size of each data beat (byte, halfword, word, and wider).
• HBURST — the burst type: a single beat or a multi-beat burst, and its shape (SINGLE, INCR, WRAP — detailed in Module 3).
• HPROT — protection/attribute hints about the access (privilege, cacheability, and similar).

The key realization is that the address phase carries everything about the access except the payload. By the end of this single cycle, the decoder knows which subordinate is targeted and the subordinate knows exactly what is being asked of it — so the data can move next cycle. The address phase is, in effect, the manager filling out a complete request slip before any goods change hands.

2. Why Does It Exist?

The address phase exists for one decisive reason: the subordinate cannot move data until it knows it is the target and what is being asked — and finding that out takes a clock cycle.

Recall the architecture. When a manager presents an address, the decoder must examine it and select a subordinate; the selected subordinate must recognize its select and prepare to respond. That decode-and-prepare work is real logic with real propagation delay, and it needs a cycle to settle. If the manager tried to present the address and move data in the same instant, the subordinate would be asked to accept or produce data before it even knew the access was for it. That cannot work.

So splitting the transfer into address-then-data is not a stylistic choice — it is the mechanism that gives the decode and the subordinate setup their cycle. The address phase is that cycle. And this is exactly the root of the two-phase pipeline you met in the mental-model chapter: because the address phase of the next transfer can overlap the data phase of the current one, the bus stays busy. The address phase exists to make decoding possible, and its separateness is what makes pipelining possible — one decision, two payoffs.

There is a second, quieter reason: by putting the full description of the access in its own phase, the subordinate gets a clean, stable cycle to read all of it — address, direction, size, burst — before committing to the data movement. The address phase is a well-defined moment where "what is being asked" is guaranteed stable and complete.

3. Mental Model

Model the address phase as handing over a completed order form one beat before the goods move.

Picture a counter. In the first beat, you slide across a fully filled-in order form: the item's location (HADDR), whether you are dropping off or picking up (HWRITE), whether this is a one-off or the first of a series (HTRANS), how big each item is (HSIZE), and whether a batch is coming and in what pattern (HBURST). You hand over only the form — no goods yet. The clerk reads the form, walks to the right shelf (the decoder selecting the subordinate), and gets ready. In the next beat, the goods actually move. The form always precedes the goods by one beat, because the clerk needs that beat to read it and get to the right shelf.

Now watch the timing of a real pair of transfers, which is the heart of this chapter:

The model makes the chapter's two big ideas visible: the form precedes the goods (address phase precedes data phase for each transfer), and forms and goods overlap across transfers (while A's goods move, B's form is already handed over). That overlap is the pipeline, and the address phase is the half that makes it work.

4. Real Hardware Perspective

In hardware, the address phase is a single clock cycle in which the manager's address and control outputs are driven and held stable for the subordinate and decoder to sample.

The manager registers its address-phase outputs so they are stable for the whole cycle, because the decoder is combinationally decoding HADDR and the subordinate is sampling the control signals. Stability matters: if HADDR glitched mid-cycle, the decoder could momentarily select the wrong subordinate. So the address phase is, in timing terms, a cycle where a known-stable address and control set are presented, the decoder's combinational logic resolves a selection within that cycle, and the selected subordinate latches what it needs.

A crucial hardware consequence appears when the access is stalled (which happens via the ready mechanism, the subject of the next chapter): the address-phase information must remain valid until the access actually completes. If the subordinate inserts wait states, the manager continues to hold the address-phase control so the access stays well-defined throughout the wait. In other words, the "address phase" is one cycle in the simple case, but its information governs the access until the data phase finishes — the description cannot evaporate while the access is still in flight.

This is also where the HADDR-to-decoder path sets a real timing constraint. The address must propagate from the manager, through the decoder's combinational logic, to the subordinate's select, all within the address-phase cycle, so that the subordinate is ready to act in the data phase. On larger systems this decode path can be a timing-critical signal, which is one reason address maps and decoders are designed with care — the whole pipeline depends on the address being decoded inside its cycle.

5. System Architecture Perspective

At the system level, the address phase is where the chip's address map meets the bus in real time — it is the moment the decoder turns an address into a subordinate selection, every single access.

Because the decoder reads HADDR in the address phase, the address map you defined as an architecture document becomes live logic in this cycle: the range a subordinate owns is exactly the set of HADDR values that make the decoder select it. So the address phase is where "the memory map" stops being a spreadsheet and becomes a routing decision. Every access re-evaluates it: present an address, get a subordinate. This is why a wrong address map or a buggy decoder shows up as accesses landing on the wrong subordinate — the error is realized in the address phase.

The address phase also carries the intent signals that the rest of the system uses for more than routing. HSIZE and HBURST tell a memory how to handle the access efficiently; HPROT carries protection and cacheability hints that a system might use for access control or memory-attribute decisions. So the address phase is not only "where do I go?" but "what kind of access is this?", and system-level features — protection units, memory controllers optimizing for burst patterns — read these address-phase signals to do their jobs. The richness of the address phase is what lets the system make informed decisions before any data moves.

Finally, the address phase is the natural place to think about the default subordinate from the terminology chapter. If HADDR in the address phase matches no real subordinate's range, the decoder selects the default subordinate, which will complete the access (typically with an error) rather than letting it hang. So the safety net for bad addresses is engaged precisely here, in the decode of the address phase.

6. Engineering Tradeoffs

The address phase embodies a few tradeoffs worth naming, mostly around how much is decided up front.

• Rich description vs signal count. AHB's address phase carries a lot — address, direction, type, size, burst, protection. This richness lets subordinates and memory controllers prepare and optimize, but it means more control wires than a minimal bus like APB. AHB pays the wires to make the access fully self-describing before data moves — a good trade for a performance bus.
• Decode-in-a-cycle vs map complexity. Requiring the decode to resolve within the address-phase cycle keeps the pipeline tight, but it bounds how complex the address map and decoder can be before the decode path becomes timing-critical. Fine-grained maps give cleaner separation but stress this path; coarse maps are easier to time. The tradeoff is map precision versus decode timing.
• Commit-up-front vs flexibility. Because the full access is described in the address phase, the subordinate can prepare optimally — but it also means the manager commits to the access's shape before the data phase. AHB does not let you "change your mind" about size or direction mid-access; the address phase fixes them. This rigidity buys simplicity and predictability.
• Pipelining benefit vs hold obligation. Separating the address phase enables pipelining (its overlap with the previous data phase keeps the bus busy), but it imposes the obligation to hold address-phase information stable across any wait states. The benefit (throughput) comes with a discipline (stable hold), and getting the hold wrong is a classic source of bugs.

The through-line: the address phase front-loads the full description of the access, which is what makes decoding, preparation, and pipelining all possible — at the cost of more control signals and the discipline to keep them stable. It is a deliberate "describe completely, then execute" design.

7. Industry Example

Trace the address phase of a concrete access and watch each signal do its job.

A processor (manager) issues a single 32-bit read from an on-chip peripheral whose registers live behind the AHB. In the address phase:

• The processor drives HADDR with the peripheral register's address, HWRITE low (a read), HTRANS indicating a real non-sequential access, HSIZE indicating a word, and HBURST indicating a single (non-burst) transfer.
• The decoder reads HADDR, recognizes it falls in the peripheral's range, and asserts that subordinate's select; every other subordinate sees it is not selected and stays inert. The same selection sets up the multiplexor to route this subordinate's read data back next cycle.
• The peripheral subordinate, now selected, reads the control signals: it sees a word-sized read and prepares to drive the register's value. It has a full cycle to do this before the data phase.
• If the peripheral can respond immediately, the data phase next cycle simply moves the read data back. If it needs time, it will insert wait states in the data phase — but throughout, the processor holds the address-phase control stable so the access stays well-defined.

Now picture a pipelined pair: while this read's data phase is happening, the processor is already presenting the next access's address phase — say a write to a different register. The decoder is already selecting that next subordinate while the current one is still returning its read data. The address phase of the second access overlaps the data phase of the first, and the bus never idles between them. Every signal in the address phase — address for routing, direction and size and burst for preparation — is doing exactly the job that lets the subordinate be ready the moment the data phase arrives. That readiness, bought one cycle early, is the entire purpose of the address phase.

8. Common Mistakes

9. Interview Insight

"What happens in the AHB address phase?" is a standard signal-level question, and a precise answer shows you have crossed from concept to mechanism.

The answer that lands names the signals by role, the decoder's action, and the reason: "In the address phase the manager drives HADDR plus the control signals — HWRITE, HTRANS, HSIZE, HBURST — fully describing the access, with no data yet. The decoder reads HADDR and selects the subordinate, which prepares to respond. The phase exists because decode and setup take a cycle, so address must precede data — and that separation is what lets the next transfer's address phase overlap this one's data phase." Add the hold rule — control stays stable across wait states — and you have shown signal-level command.

10. Practice Challenge

Reason at signal level, using roles rather than encodings.

1. List the address-phase signals. From memory, name the signals the manager drives in the address phase and give each a one-line role. Check against Figure 1.
2. Defend the ordering. In three sentences, explain why the address phase must precede the data phase, referencing decode and subordinate setup.
3. Read the waveform. Using Figure 3, identify which cycle is access A's address phase, which is its data phase, and where access B's address phase overlaps.
4. Apply the hold rule. A subordinate stalls a transfer for two extra cycles. State exactly what the manager does with its address-phase signals during those cycles and why.
5. Spot the bug. A manager changes HADDR one cycle into a stalled access. Describe the failure and name the rule it violates.

11. Key Takeaways

• The address phase is the first cycle of an AHB transfer, in which the manager drives the full description of the access — HADDR, HWRITE, HTRANS, HSIZE, HBURST (plus HPROT) — with no data yet.
• It carries everything except the payload. If it describes the access, it is address-phase; if it is the data or completion, it is data-phase.
• It exists because decode and subordinate setup take a cycle: the subordinate cannot move data until the decoder has selected it from HADDR. The phase is that cycle.
• Its separateness enables pipelining — the next transfer's address phase overlaps the current transfer's data phase, keeping the bus busy.
• The hold rule: address-phase control must stay stable across any wait states until the access completes. Changing it mid-access is a classic corruption bug.
• The address phase is where the address map becomes live logic — the decoder turns HADDR into a subordinate selection every access, and engages the default subordinate for unmapped addresses. Bit-level encodings come in Module 3.

12. What Comes Next

You now know the first half of every AHB transfer. The next chapter completes the pair — the data phase, where the payload actually moves and the subordinate signals completion:

• 2.4 — The Data Phase (coming soon) — how read and write data move, gated by HREADY, and how the subordinate signals completion and response.
• 2.5 — Pipelined Operation (coming soon) — the address and data phases overlapping in full, at signal level.

To revisit the structure and components behind this phase, see AHB Bus Architecture and Master, Slave, Decoder & Arbiter. For the model it realizes, see The AHB Mental Model. For the broader protocol map, see the AMBA family overview.