Clock Gating Considerations

This chapter turns from reset to clocking — specifically, clock gating: stopping HCLK to save power, without corrupting transfers. Clock gating is a major dynamic-power saver (no clock → no switching), but on AHB it has two hard rules. (1) Gate only when the bus is idle — when the bus is quiescent (HTRANS = IDLE, HREADY high, no transfer in flight). Gating the clock mid-transfer freezes that transfer in an incomplete state — neither the master nor the slave can advance without the clock — hanging the bus. So gate only at idle boundaries, and ungate before the next transfer needs to start. (2) Use a glitch-free gate — gate with an integrated clock-gating cell (ICG) that latches the enable on the clock-low phase, not a bare AND of the clock and an enable. A plain AND can glitch — if the enable changes while the clock is high, the gated clock produces a runt pulse that corrupts flip-flops. The ICG ensures the gated clock only ever turns on/off cleanly (whole pulses, no glitches). This chapter covers the gate-when-idle rule and the glitch-free-gating requirement — the two considerations for safe HCLK gating.

1. What Is It?

Clock gating is stopping HCLK (the AHB clock) when the bus isn't in use, to save dynamic power. The two safety considerations:

• Gate only when idle — gate only when the bus is quiescent: HTRANS = IDLE, HREADY high, no transfer in flight. Ungate before the next transfer.
• Never gate mid-transfer — gating during a transfer freezes it (no clock → no progress), hanging the master and slave.
• Use a glitch-free gate — an integrated clock-gating cell (latches the enable on the clock-low phase), not a bare AND (which can produce a corrupting runt pulse).

So clock gating is a power technique with correctness constraints. The power benefit is real (HCLK drives a lot of switching logic — gating it when idle saves significant dynamic power). But the correctness rules are strict: you can only gate when there's nothing in flight (idle), because a transfer needs the clock to progress (every phase advances on a clock edge) — stopping the clock mid-transfer freezes it indefinitely (the master waits for the slave, the slave waits for the next edge, neither advances). And the gate itself must be glitch-free — a clock glitch (runt pulse) can clock flops at the wrong time, corrupting state. So clock gating is "gate when idle, ungate before the next transfer, with a glitch-free cell." So it's the safe stopping of HCLK to save power.

2. Why Does It Exist?

Clock gating exists because dynamic power scales with clock activity, so stopping the clock when idle saves significant power — but it has the idle-only and glitch-free rules because a transfer requires the clock to progress (so gating mid-transfer hangs it) and a clock glitch corrupts state (so the gate must be clean).

The power motivation is the root: dynamic power in CMOS scales with the clock activity — every clock edge causes flip-flops and clock-tree buffers to switch, dissipating power. HCLK drives a lot of logic (all the masters, slaves, interconnect flops, the clock tree). When the bus is idle (no transfers), that switching is wasted — the clock toggles but nothing useful happens. So stopping HCLK when idle saves that wasted dynamic power (a major saving — the bus/clock-tree power can be significant). So clock gating exists to eliminate wasted dynamic power during idle. So it's a key low-power technique.

The gate-only-when-idle rule exists because transfers need the clock: an AHB transfer progresses on clock edges — the address phase advances to the data phase on an edge, the slave samples on edges, HREADY is evaluated on edges. So without the clock, a transfer can't progress — it's frozen. If you gate the clock mid-transfer, the transfer freezes incomplete — the master is waiting for the slave's response (which needs a clock edge to come), the slave is waiting to advance (which needs an edge) — deadlock (the bus hangs, indefinitely, until the clock returns). So you must not gate mid-transfer — only when idle (nothing in flight to freeze). So the idle-only rule exists because gating a transfer freezes it. So gate only quiescent.

The glitch-free rule exists because a clock glitch corrupts state: clock-gating logic combines the clock with an enable. If done with a bare AND (gated = clk AND enable), and the enable changes while the clock is high, the gated clock output produces a partial/runt pulse (a brief, malformed clock edge). A runt pulse can clock the flip-flops at the wrong time (or cause metastability) — corrupting their state. So the gate must be glitch-free: an integrated clock-gating cell latches the enable on the clock-low phase (when the clock is low, so a change can't create a partial high pulse), ensuring the gated clock only cleanly turns on or off (whole pulses). So the glitch-free rule exists to prevent clock glitches corrupting state. So use a proper gate. So clock gating exists because: dynamic power scales with clock activity, so gating the idle clock saves wasted power (the why); it must be gated only when idle because a transfer needs the clock to progress (gating mid-transfer freezes/hangs it — the correctness rule); and the gate must be glitch-free (an ICG, not a bare AND) because a clock glitch corrupts state (the implementation rule). So clock gating is the power-saving technique constrained by these two correctness rules — gate idle-only, with a clean gate. So this chapter is how to gate safely.

3. Mental Model

Model clock gating as turning off a factory's main conveyor to save power — you can shut it down between batches when nothing's on the belt (gate when idle), saving the motor's energy; but you must never stop it mid-batch with products halfway through (gate mid-transfer) — they'd be stranded incomplete, jamming the line (hang); and you must shut the motor down cleanly with a proper controller, not by flickering the power switch (which could jolt the belt and damage products — a clock glitch) — so use the designed shutdown sequence that stops the belt smoothly at a safe point.

A factory's main conveyor (HCLK) drives the whole line — running it costs motor energy (dynamic power). To save energy, you can shut it down — but only at the right times and the right way. You can shut it down between batches, when nothing's on the belt (the bus is idle — no transfer in flight) — that's safe, and saves the motor's energy during the lull (gate when idle). But you must never stop the conveyor mid-batch, with products halfway through (a transfer in flight) — they'd be stranded incomplete, jamming the line, and nothing can move until the belt restarts (gating mid-transfer freezes the transfer, hanging the bus — no clock, no progress). And crucially, you must shut the motor down cleanly — using the designed shutdown controller that stops the belt smoothly at a safe point — not by flickering the power switch on and off (which could jolt the belt, damaging products mid-handling — a clock glitch / runt pulse corrupting flops). So the rule: shut down between batches (idle), cleanly (glitch-free controller), and restart before the next batch (ungate before the next transfer). Stop at the lulls, smoothly, never mid-batch.

This captures clock gating: the conveyor motor = HCLK; its energy cost = dynamic power; shutting down between batches = gating when idle; products mid-belt stranded = a transfer frozen mid-flight; jamming the line = hanging the bus; flickering the power switch jolting the belt = a bare-AND clock glitch / runt pulse; the designed clean shutdown controller = the glitch-free clock-gating cell; restarting before the next batch = ungating before the next transfer. Stop at the lulls, smoothly, never mid-batch.

Watch HCLK gated during idle, ungated before a transfer:

The model's lesson: stop at the lulls, smoothly, never mid-batch. In the waveform, HCLK is gated only during the idle window and ungated before the transfer — saving power without freezing any transfer.

4. Real Hardware Perspective

In hardware, clock gating uses an integrated clock-gating (ICG) cell driven by an idle-detect enable, placed in the clock tree to the bus logic — gating the bus's HCLK when idle and ungating it on a wake event.

The ICG cell is the glitch-free gate: a standard-cell integrated clock-gating cell takes the clock and an enable, and produces the gated clock. Internally, it latches the enable on the clock-low phase (a level-sensitive latch on the inactive clock phase) — so the enable can only take effect when the clock is low, guaranteeing the gated clock has whole pulses (no runt/partial pulses). So the ICG is the standard, glitch-free way to gate a clock. So in hardware, always use an ICG (synthesis tools insert them; never hand-build a bare-AND gate). So the ICG ensures clean gating.

The idle-detect enable: the ICG's enable comes from idle-detect logic that determines when the bus is quiescent — no transfer in flight (HTRANS = IDLE, HREADY high, no outstanding response, no pending request). When idle for some period (or immediately, per the policy), the idle-detect deasserts the enable → the ICG gates the clock. On a wake event (a new transfer to issue, an interrupt, a master request), the idle-detect asserts the enable → the ICG ungates — before the transfer starts. So in hardware, the gating is driven by idle-detect, with wake-up ungating before activity. So the enable encodes "the bus is idle." So gating tracks the bus's activity.

The placement and granularity: the ICG is placed in the clock tree feeding the bus logic (the masters/slaves/interconnect flops). Gating can be at various granularities — the whole bus subsystem (gate HCLK to everything when fully idle), or per-block (gate an idle slave's clock while others run). Finer granularity saves more power (gate each idle block independently) at more idle-detect logic. So in hardware, clock gating is an ICG in the clock tree, driven by idle-detect, at a chosen granularity. So the hardware: ICG cells (glitch-free) gated by idle-detect (quiescent-bus enable), ungated on wake before activity, placed in the clock tree at the chosen granularity — saving dynamic power during idle without ever freezing a transfer. So in hardware, safe gating is "ICG + idle-detect + ungate-before-activity." So the hardware reality: gate the idle clock cleanly, wake before you need it.

5. System Architecture Perspective

At the system level, clock gating is the primary fine-grained dynamic-power technique — applied throughout the SoC's clock trees — and the AHB-specific rules (gate-when-idle, glitch-free) are instances of the universal clock-gating discipline.

The primary dynamic-power technique: clock gating is the most common, fine-grained way to reduce dynamic power in a synchronous SoC. The clock tree and the flops it drives are a major dynamic-power consumer — and much of the time, large parts of the chip are idle. Gating the idle clocks eliminates that wasted switching. So clock gating is applied pervasively — to the bus, to idle peripherals, to idle subsystems, to fine-grained logic (synthesis tools auto-insert clock gates on registers with enables). So at the system level, clock gating is the go-to dynamic-power technique, and AHB clock gating is one application of it. So it's everywhere.

The AHB rules as universal principles: the AHB clock-gating rules — gate only when idle (don't freeze in-flight activity) and use a glitch-free gate (ICG, not bare AND) — are not AHB-specific; they're the universal clock-gating discipline. Gate-when-idle generalizes: gate any clock only when the logic it drives is quiescent (no in-flight operation that needs to progress) — gating active logic freezes it. Glitch-free generalizes: always gate with an ICG (the bare-AND glitch problem is universal). So the AHB rules teach the general clock-gating principles. So at the system level, AHB clock gating exemplifies the universal discipline — applicable to any clock domain. So it's a transferable principle.

The part of the low-power strategy: clock gating is one layer of the SoC's low-power strategy — alongside power gating (turning off power to idle blocks — saves leakage too, but slower to wake), voltage/frequency scaling (DVFS — lower V/f for lower power), and clock gating (stop the clock — saves dynamic, fast to wake). Clock gating is the fastest, finest (gate/ungate in cycles, no state loss) but only saves dynamic power (not leakage). So at the system level, clock gating is the fine-grained, fast, dynamic-power layer of the low-power strategy — used for short idle periods (gate/ungate quickly), with power gating for longer idle (worth the slower wake to save leakage). So clock gating fits a hierarchy of power techniques. So at the system level, clock gating is the primary fine-grained dynamic-power technique (applied pervasively, including to the AHB bus), the AHB rules (gate-when-idle, glitch-free) exemplify the universal clock-gating discipline (transferable to any clock), and it's the fast, fine layer of the broader low-power strategy (clock gating for dynamic/short-idle, power gating for leakage/long-idle, DVFS for scaling). The next chapter (15.5, low-power implications) builds on this to the full strategy. So clock gating is where AHB meets the SoC's power management — saving dynamic power safely.

6. Engineering Tradeoffs

Clock gating embodies the gate-idle-only, glitch-free, dynamic-power design.

• Gate when idle (power saving) vs always-on. Gating the idle clock saves dynamic power at the cost of idle-detect logic and ungate latency; always-on wastes power during idle. Gate when idle.
• Never gate mid-transfer. Gating only at idle boundaries is required for correctness (gating mid-transfer hangs the bus). There's no tradeoff here — it's a hard rule.
• Glitch-free ICG vs bare AND. An ICG (latch enable on clock-low) is glitch-free (correct) at the cost of the cell; a bare AND is "simpler" but glitches (corrupts flops). Always use an ICG — no tradeoff (bare AND is just wrong).
• Fine vs coarse gating granularity. Per-block gating (gate each idle block independently) saves more power at more idle-detect logic; coarse (gate the whole bus when fully idle) is simpler but saves less. Choose per the power target.

The throughline: clock gating stops HCLK when the bus is idle to save dynamic power — but only when the bus is quiescent (HTRANS = IDLE, HREADY high, no transfer in flight), and ungated before the next transfer; gating mid-transfer freezes the transfer and hangs the bus. The gate must be glitch-free — an integrated clock-gating cell (latches the enable on the clock-low phase → whole pulses, no runt pulses), not a bare AND (which glitches and corrupts flops). In hardware: an ICG in the clock tree, driven by idle-detect, ungated on wake before activity, at a chosen granularity. It's the primary fine-grained dynamic-power technique, exemplifying the universal clock-gating discipline, and the fast/fine layer of the SoC's low-power strategy.

7. Industry Example

Apply clock gating to an idle MCU peripheral subsystem.

An MCU gates the clock to its peripheral bus when idle to save power.

• Idle detection. The peripheral subsystem (behind the bridge) is idle most of the time (peripherals are accessed infrequently). Idle-detect logic monitors the bus: when there's no transfer in flight (HTRANS = IDLE, HREADY high, no pending access), the subsystem is quiescent.
• Gate when idle. When quiescent, the idle-detect deasserts the clock-gating enable → the ICG gates the peripheral subsystem's clock (HCLK to those peripherals stops). The peripherals' flops stop switching — dynamic power saved during the (long) idle.
• Glitch-free. The gate is an integrated clock-gating cell — the enable is latched on the clock-low phase, so when the clock gates/ungates, it does so cleanly (whole pulses, no runt). No flop corruption.
• Wake before access. When the CPU needs to access a peripheral (a new transfer), the idle-detect (or the access decode) asserts the enable first → the ICG ungates the peripheral clock — before the transfer reaches the peripheral. So the clock is running when the peripheral must respond. The wake-up latency (a cycle or two for the ungate) is accounted for.
• Never mid-transfer. Crucially, the gating only happens when the subsystem is idle. If a transfer is in flight to a peripheral, the clock is kept running until it completes — the gating logic won't gate a busy subsystem. So no transfer is ever frozen.
• The bug avoided. Had the design (mistakenly) gated the clock while a peripheral transfer was in flight, that transfer would freeze — the CPU would hang waiting for the peripheral's HREADY (which can't come without the clock). The idle-only rule prevents this. And had it used a bare AND gate, the gate toggling could glitch and corrupt a peripheral's state — the ICG prevents this.

The example shows safe clock gating: idle-detect gates the quiescent peripheral clock (saving dynamic power during the long idle), with a glitch-free ICG, ungating before any access (wake-up before activity), and never gating a busy subsystem (no frozen transfers). This is how clock gating saves power on an AHB subsystem without corrupting transfers.

8. Common Mistakes

9. Interview Insight

Clock gating is a low-power interview topic — the gate-when-idle rule (and why mid-transfer hangs), and the glitch-free-ICG requirement are the signals.

The answer that lands gives both rules with reasoning: "Clock gating stops HCLK to save dynamic power, but there are two hard rules. First, you can only gate the clock when the bus is idle — HTRANS = IDLE, HREADY high, no transfer in flight — and you must ungate before the next transfer. The reason is that an AHB transfer progresses on clock edges: the address phase advances to the data phase on an edge, the slave samples on edges, HREADY is evaluated on edges. So without the clock, a transfer can't progress — it's frozen. If you gate the clock mid-transfer, that transfer is stuck incomplete forever: the master waits for the slave's response, which needs a clock edge to arrive, and the slave can't advance without an edge — the bus hangs. So you only gate when the bus is quiescent, with nothing in flight. Second, the gate itself must be glitch-free: you use an integrated clock-gating cell, which latches the enable on the clock-low phase, so the gated clock only ever turns on or off cleanly — whole pulses, no runt pulses. You must not use a bare AND of the clock and an enable, because if the enable changes while the clock is high, the AND produces a partial, runt pulse that can clock the flops at the wrong time and corrupt their state. So the two considerations are: gate only at idle boundaries, ungating before activity resumes, and gate with a proper glitch-free clock-gating cell. And these are universal clock-gating rules, not AHB-specific." The gate-when-idle rule (with the freeze reasoning) and the glitch-free-ICG requirement are the senior signals.

10. Practice Challenge

Reason from clock gating.

1. The two rules. State the two safety rules for clock gating (gate-when-idle, glitch-free).
2. Why idle-only. Explain why gating mid-transfer hangs the bus.
3. Read the waveform. From Figure 2, explain how HCLK is gated during idle and ungated before the transfer.
4. Glitch-free. Explain why a bare AND gate glitches and how an ICG avoids it.
5. Strategy. Place clock gating in the broader low-power strategy (vs power gating, DVFS).

11. Key Takeaways

• Clock gating stops HCLK when idle to save dynamic power — but only when the bus is quiescent (HTRANS = IDLE, HREADY high, nothing in flight), and ungated before the next transfer.
• Never gate mid-transfer — a transfer progresses on clock edges, so stopping the clock freezes it (no progress), hanging the bus (a deadlock). Gate at idle boundaries only.
• Use a glitch-free clock-gating cell (ICG) — it latches the enable on the clock-low phase (whole pulses, no runt) — not a bare AND (which glitches if the enable changes while the clock is high, corrupting flops).
• Both rules are correctness requirements — mid-transfer gating hangs the bus (intermittent deadlock); a bare-AND gate intermittently corrupts state. Classic, avoidable bugs.
• In hardware: an ICG in the clock tree, driven by idle-detect (quiescent-bus enable), ungated on wake before activity, at a chosen granularity.
• It's the primary fine-grained dynamic-power technique — fast, fine, state-preserving — the fast layer of the low-power strategy (clock gating for dynamic/short-idle; power gating for leakage/long-idle; DVFS for scaling). The AHB rules are universal clock-gating principles.

12. What Comes Next

You now understand clock gating — gate when idle, glitch-free, to save dynamic power. The next chapters cover the broader power picture and crossing clock domains:

• Low-Power Implications (next) — relating AHB activity to SoC power and the gating strategy.
• CDC Bridges — bridging AHB across asynchronous clock domains safely.

To revisit the idle state you gate at, see HTRANS & Bus Control; for the reset foundation, see HRESETn Behavior.