VHDL tutorials & labs.
VHDL from foundations to advanced — entities, architectures, packages, generics, and rigorous testbenches.
Tutorials
Learn VHDL from beginner to advanced through structured tutorials.
Labs
Practice VHDL using progressively challenging hands-on labs.
What VHDL is
VHDL is a strongly typed hardware description language built around a simple split: an entity declares the interface a block presents to the outside world, and an architecture describes what happens inside it. Inside an architecture, concurrent statements and processes all execute simultaneously, modelling hardware rather than a program. The type system is the language's defining trait — a signal has an explicit type, widths must match, and conversions are written out rather than assumed. Standardised as IEEE 1076, VHDL remains the primary HDL across European industry, aerospace, defence and much FPGA work.
Why it exists
VHDL was designed so that a hardware description could be read, simulated and checked long before anyone committed to silicon, and its type system exists to catch a whole class of mistakes at compile time rather than in a waveform at 2 a.m. Connecting a 7-bit signal to an 8-bit port is an error you are told about immediately, not a truncation you discover during debug. The verbosity people complain about is largely the price of that strictness — and on a large team, catching interface mismatches at compile time is usually worth the extra typing.
The part engineers get wrong
The distinction that causes the most beginner bugs is signals versus variables. A variable, assigned with :=, updates immediately: the next line inside the same process sees the new value. A signal, assigned with <=, schedules its update, so within one process pass every read still returns the OLD value no matter where the assignment appeared. Write a counter with a variable and you get combinational chaining; write it with a signal and you get a register. The rule to carry is that a signal assignment is a promise about the future, not an instruction executed now.
Before you start
- Digital logic: gates, flip-flops and clocked behaviour
- Binary and hexadecimal representation
- No prior HDL experience assumed
What you will be able to do
- Declare an entity and architecture, and connect components into a hierarchy
- Choose between a signal and a variable, and predict when each updates
- Write processes that synthesise into the combinational or sequential logic you intended
- Use generics to parameterise a design by width or depth
- Organise shared types and constants into packages
- Model a finite state machine and write a testbench that checks it
The learning path
- Entity and architectureThe interface/implementation split every VHDL design starts from
- Types and signalsStrong typing, signals as wires, and why widths must match
- Concurrent statementsAssignments that all happen at once, like real hardware
- ProcessesSequential regions, sensitivity lists and when they wake
- Signals vs variablesThe update-timing difference that decides your hardware
- Generics and packagesParameterising designs and sharing declarations
- RecordsGrouping related signals into a single composite interface
- State machinesEncoding state and separating next-state from output logic
- TestbenchesDriving stimulus and checking results in simulation
Core concepts
New to VHDL? Work through the curriculum in order — each lesson assumes the one before it, and the sequence is what turns the roadmap above into working knowledge.
Already working with it? Use the core-concept links above to jump straight to the topic you need; each one opens the lesson that covers it in most depth.
Where this leads
Standards: IEEE 1076 — The VHDL language standard this track is authored against