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AMBA AHB · Module 8

WRAP4 & INCR4 Bursts

The AHB 4-beat fixed-length bursts — INCR4 (four linear incrementing beats) and WRAP4 (four beats wrapping within the aligned 4-beat block) — with the concrete wrap mechanics and why WRAP4 serves critical-word-first cache line fills.

Chapter 8.3 covered the undefined-length INCR. This chapter covers the first fixed-length pair: INCR4 and WRAP4 — both 4-beat bursts, and the place to learn the wrapping mechanics concretely. INCR4 is four linearly-incrementing beats. WRAP4 is four beats that wrap within an aligned block of size 4×beat-size — the address increments but, on reaching the block boundary, wraps back to the block's start. The concrete difference: a WRAP4 of words starting at 0x08 goes 0x08 → 0x0C → 0x00 → 0x04 (wrapping at the 16-byte boundary), while an INCR4 from 0x08 goes 0x08 → 0x0C → 0x10 → 0x14 (crossing the boundary). WRAP4 exists for 4-word cache line fills: critical-word-first, staying within the aligned line. Understanding the wrap math here sets up WRAP8/16 (chapters 8.5–8.6).

1. What Is It?

INCR4 and WRAP4 are both 4-beat fixed-length bursts (HBURST declares the 4-beat count up front), differing in the address pattern:

  • INCR4 — four beats, address incrementing linearly (each beat = previous + beat size). It can cross an aligned boundary.
  • WRAP4 — four beats, address incrementing but wrapping within the aligned block of size 4 × beat-size. On reaching the block boundary, the address wraps to the block's start, keeping all four beats inside the one aligned block.
Two address sequences from 0x08: INCR4 going 0x08/0x0C/0x10/0x14 (crossing the boundary), WRAP4 going 0x08/0x0C/0x00/0x04 (wrapping within the 16-byte block).
Figure 1 — INCR4 vs WRAP4, four word beats starting at 0x08. INCR4 increments linearly: 0x08, 0x0C, 0x10, 0x14 — crossing the 16-byte boundary at 0x10 into the next block. WRAP4 wraps within the aligned 16-byte block (0x00–0x0F): 0x08, 0x0C, then wraps back to 0x00, 0x04. WRAP keeps the four words inside one aligned block — what a cache line fill needs; INCR spills into the next block.

The wrap math for WRAP4: the aligned block has size 4 × beat-size (for words, 4 × 4 = 16 bytes). The address increments by the beat size each beat, but the lower address bits (those within the block) wrap, while the upper bits (the block's base) stay fixed. So a WRAP4 of words is confined to its aligned 16-byte block: starting anywhere in the block, it visits all four words, wrapping at the boundary. INCR4, by contrast, just increments and can cross the boundary into the next block. Both are exactly 4 beats (fixed length); the difference is purely whether the address wraps within the aligned block (WRAP4) or increments past it (INCR4).

2. Why Does It Exist?

The 4-beat fixed-length bursts exist because 4-beat blocks are common (especially 4-word cache lines), and declaring the fixed count gives memory the precise prefetch a known-size block allows — while WRAP4 specifically exists to serve the critical-word-first cache line fill pattern.

The fixed-length aspect (versus undefined INCR) is about precision: when you're moving a known 4-beat block, declaring "exactly 4 beats" lets the memory controller prefetch precisely those 4 beats (chapter 8.1) — better than INCR's speculative prefetch. So INCR4/WRAP4 exist for known-size 4-beat transfers where the exact-count prefetch is worth declaring the length. A 4-word cache line is exactly such a known block. So the 4-beat fixed types serve known 4-beat blocks with precise prefetch.

The WRAP4 wrapping specifically exists for the cache line fill. When a CPU cache misses on a word, it fetches the whole cache line — but it wants the missed (critical) word first (so the CPU can resume as soon as that word arrives), then the rest of the line. And a cache line occupies an aligned block. WRAP4 delivers exactly this for a 4-word line: start at the critical (missed) word, increment, and wrap at the aligned line boundary to fetch the remaining words — so the whole aligned line is fetched, critical-word-first.

A 4-word cache line with a miss at 0x08, and the WRAP4 fetch order 0x08, 0x0C, 0x00, 0x04 delivering the critical word first and wrapping within the aligned line.
Figure 2 — WRAP4 serves a 4-word cache line fill, critical-word-first. A 4-word line is an aligned 16-byte block. On a miss for the word at 0x08, the cache wants that critical word first, then the rest, wrapping at the line boundary. WRAP4 delivers 0x08 (critical), 0x0C, then wraps to 0x00, 0x04 — the whole aligned line, critical-word-first. The CPU resumes as soon as 0x08 arrives while the rest of the line fills behind it.

The reason INCR (linear) can't serve the cache fill as cleanly is that it doesn't wrap — starting at the critical word 0x08 and incrementing linearly would go 0x08, 0x0C, 0x10, 0x14, leaving the aligned line (0x00–0x0F) and fetching words outside it (0x10, 0x14) while missing the words before the critical one (0x00, 0x04). That's wrong for a cache line — you'd fetch the wrong words. So to get critical-word-first and stay within the aligned line, you need wrapping — which is exactly why WRAP4 exists. INCR4 serves linear 4-beat blocks (where you do want to march straight through); WRAP4 serves cache lines (where you need critical-word-first within the aligned line). The two 4-beat types serve the two patterns.

3. Mental Model

Model WRAP4 versus INCR4 as reading a 4-seat round table starting from your seat — you go around the table (wrapping back to seat 1 after seat 4) to visit everyone, versus walking down a straight row of seats (just continuing past the end into the next row).

Imagine a round table with 4 seats (the aligned 4-beat block). You want to greet everyone, starting from your seat (the critical word). Going around the table (WRAP4), you greet your neighbor, then the next, and when you reach the "end," you wrap around back to seat 1 and continue — so you visit all 4 seats at this table, starting from yours. That's the cache-line pattern: start at the critical word, go around, stay at this table (this aligned line). Contrast a straight row of seats (INCR4): starting from your seat, you just keep walking down the row, past the end of your group and into the next group's seats — you don't come back to greet the people before you. That's fine for a linear walk (a linear block), but wrong if you wanted to greet everyone at your table — for that you must go around (wrap).

This captures the distinction: going around the round table = WRAP4 (wrap within the aligned block, visit all 4 starting from the critical one); walking down the straight row = INCR4 (increment linearly, can leave the block). The round table (bounded, you come back around) is the cache line; the straight row (open-ended direction) is a linear block. WRAP keeps you at your table; INCR walks straight on.

Watch a WRAP4 wrap:

A WRAP4 burst wrapping within the aligned block

4 cycles
HBURST is WRAP4. HTRANS is NONSEQ then SEQ, SEQ, SEQ. HADDR goes 0x08, 0x0C, then wraps to 0x00, then 0x04 — staying within the aligned 16-byte block. The wrap shows as the address dropping from 0x0C back to 0x00.0x0C — at the block's top word0x0C — at the block's …wraps at 0x10 boundary → 0x00 (stays in block)wraps at 0x10 boundary…HCLKHTRANSNSEQSEQSEQSEQHADDR0x080x0C0x000x04HBURSTWRAP4WRAP4WRAP4WRAP4t0t1t2t3
Figure 3 — a WRAP4 burst wrapping. HBURST=WRAP4, four word beats starting at 0x08. NONSEQ at 0x08, then SEQ at 0x0C, then the address wraps at the 0x10 boundary back to 0x00 (SEQ), then 0x04 (SEQ). The four beats stay within the aligned 16-byte block (0x00–0x0F), visiting all four words critical-word-first. The wrap is visible as the address jumping from 0x0C back to 0x00.

The model's lesson: WRAP4 goes around the table — it wraps at the aligned boundary to visit all four words of the block, starting from the critical one. In the waveform, the address wraps from 0x0C back to 0x00, keeping the four beats in the aligned 16-byte block. INCR4 would instead have continued to 0x10, leaving the block.

4. Real Hardware Perspective

In hardware, the difference between INCR4 and WRAP4 is purely in the manager's address generator: INCR4 adds the beat size each beat (full increment), while WRAP4 increments only the lower address bits (those within the aligned block), wrapping them, while holding the upper bits fixed.

The WRAP4 address generation is a bounded increment: the block size is 4 × beat-size, so the wrap boundary is at that alignment. The manager increments the address by the beat size each beat, but the increment is confined to the lower bits that index within the block — when those bits would overflow the block, they wrap to zero (within the block), while the upper bits (the block's aligned base) stay constant. Concretely for WRAP4 of words: the block is 16 bytes (lower 4 bits index within it), so the manager increments the lower 4 bits mod 16 (wrapping), keeping the upper bits fixed. This is simple hardware — a modular increment on the low address bits. INCR4 is a plain full-width increment (no wrap). So the address generator differs only in whether the increment wraps the low bits or carries into the high bits.

The alignment is key: a WRAP4 wraps at the boundary determined by 4 × beat-size, so the aligned block is naturally aligned to that size. This is why WRAP4 suits cache lines: a 4-word cache line is aligned to 16 bytes, exactly the WRAP4 block. So the WRAP4 boundary matches the cache line alignment by construction. The manager computes the boundary from the burst length (4) and beat size (HSIZE), and wraps the address there. The subordinate/memory, knowing it's a WRAP4, can compute the same boundary and predict the wrapped address sequence (for prefetch). So both sides understand the wrap from HBURST=WRAP4 and HSIZE.

The critical-word-first capability comes from WRAP4 being able to start anywhere in the block and wrap. The cache provides the critical (missed) word's address as the start; WRAP4 increments and wraps to cover the rest of the line. So the start address can be any word in the block, and WRAP4 visits all four starting there, wrapping. This is what gives critical-word-first: the start is the critical word. INCR4 starting at the critical word would not cover the words before it (it increments away), so INCR4 can't do critical-word-first within an aligned line — only WRAP4 can. This is the concrete hardware reason WRAP exists.

A hardware note on the fixed length (4 beats): both INCR4 and WRAP4 declare exactly 4 beats via HBURST, so the subordinate knows the burst is 4 beats (unlike undefined INCR). This lets the memory controller prefetch exactly 4 beats — and, for WRAP4, prefetch the exact wrapped sequence. So the fixed length gives precise prefetch, and the subordinate can count the 4 beats (NONSEQ + 3 SEQ) to know the burst's end (though it still watches HTRANS). The fixed count is the precision advantage of INCR4/WRAP4 over undefined INCR.

5. System Architecture Perspective

At the system level, WRAP4 is the cache-line-fill burst for 4-word lines — tightly coupled to the cache subsystem — while INCR4 serves known 4-beat linear blocks, and the choice between them maps to the access pattern (cache fill vs linear block).

WRAP4 is part of the cache subsystem's design: a CPU with 4-word (16-byte) cache lines fills them with WRAP4 bursts, critical-word-first. So WRAP4 is directly tied to the cache line size — a 4-word line uses WRAP4, an 8-word line uses WRAP8 (chapter 8.5), a 16-word line uses WRAP16 (chapter 8.6). The WRAP burst length matches the cache line size in beats. So an architect designing a cache chooses the line size, which determines the WRAP burst type used for fills. This tight coupling (cache line size ↔ WRAP length) is why WRAP bursts exist in the protocol: to serve the cache fill pattern at the various line sizes.

The critical-word-first benefit is a real performance feature: by fetching the missed word first, the CPU can resume execution as soon as that word arrives, rather than waiting for the whole line. So WRAP4 (and WRAP8/16) reduce the effective miss latency — the CPU stalls only until the critical word, not the whole line. This is a meaningful performance win for cache-heavy workloads (most CPU workloads). So WRAP's critical-word-first isn't just a nicety; it's a latency optimization the cache subsystem relies on. The system's cache miss latency is improved by WRAP's critical-word-first delivery.

INCR4 serves the other 4-beat case: a known linear 4-beat block that you want to march straight through (not wrap). For example, a fixed 4-word structure copy, or a DMA chunk of exactly 4 beats where linear order is wanted. So INCR4 is for known 4-beat linear transfers, while WRAP4 is for 4-word cache fills. The system uses each per the pattern: linear known blocks → INCR4, cache lines → WRAP4. Choosing wrong (INCR4 for a cache fill) would fetch the wrong words; (WRAP4 for a linear block) would wrap unexpectedly. So the architectural rule is to match the 4-beat type to the pattern — the same match-the-type principle as the whole burst module, now at the 4-beat granularity.

So at the system level, the 4-beat bursts split by use: WRAP4 is the 4-word cache-line-fill burst (critical-word-first, tied to the cache subsystem, improving miss latency), and INCR4 is the known 4-beat linear-block burst. The cache line size determines the WRAP length, and the access pattern determines INCR-vs-WRAP.

6. Engineering Tradeoffs

The 4-beat bursts embody the fixed-count, wrap-for-cache-lines design.

  • Fixed 4-beat vs undefined INCR. Declaring exactly 4 beats gives precise prefetch (memory knows the count) at the cost of being fixed to 4 beats. Undefined INCR is flexible but less precise. For known 4-beat blocks (cache lines), the fixed count's precision wins.
  • WRAP4 (wrap) vs INCR4 (linear). WRAP4 serves critical-word-first cache fills (wrap within the aligned line) but is constrained to the aligned block. INCR4 serves linear blocks (march straight) but can't do critical-word-first within a line. Each fits its pattern; mismatching breaks the access.
  • Critical-word-first (latency) vs simple linear (throughput). WRAP4's critical-word-first reduces CPU miss latency (resume on the critical word) at the cost of the wrapping complexity. For caches, the latency win is essential. For linear bulk movement, simple incrementing (INCR4 or INCR) suffices.
  • 4-beat granularity vs longer. A 4-beat burst is short — good for small lines/blocks and low latency, but amortizes overhead less than 8/16-beat bursts. The length matches the block size; 4-word lines use WRAP4, larger lines use WRAP8/16.

The throughline: INCR4 and WRAP4 are the 4-beat fixed-length bursts — INCR4 for known linear 4-beat blocks, WRAP4 for 4-word cache line fills (critical-word-first, wrapping within the aligned line). The fixed count gives precise prefetch; the wrap serves the cache pattern. The wrap math is a modular increment on the low address bits within the aligned 4×size block — the foundation for WRAP8/16. Match the type to the pattern: linear → INCR4, cache fill → WRAP4.

7. Industry Example

Trace the 4-beat bursts in a system with 4-word cache lines.

A CPU with 16-byte (4-word) cache lines, plus a DMA engine, move data over AHB.

  • A cache miss — WRAP4 fill, critical-word-first. The CPU misses on a load to address 0x08. Its cache line is the aligned 16-byte block 0x00–0x0F. The cache issues a WRAP4 burst starting at the critical word 0x08: 0x08, 0x0C, then wraps to 0x00, 0x04 — fetching the whole aligned line, critical-word-first. The CPU receives 0x08 first and resumes execution immediately, while 0x0C, 0x00, 0x04 fill behind it. The wrap kept the fetch within the aligned line and delivered the critical word first — reducing the miss latency.
  • The memory controller prefetches the exact line. Seeing WRAP4 (and the start address), the memory controller knows the exact 4-beat wrapped sequence and the aligned line — it fetches precisely those 4 words, efficiently. The fixed count and known wrap let it prefetch exactly.
  • A 4-word structure copy — INCR4. The DMA engine copies a fixed 4-word structure that it wants in linear order. It uses an INCR4 burst: 0x20, 0x24, 0x28, 0x2C — marching straight through the 4 words linearly (no wrap). INCR4 is right here: a known 4-beat linear block.
  • Why not swap them. If the cache used INCR4 for the fill (starting at 0x08), it would fetch 0x08, 0x0C, 0x10, 0x14 — fetching 0x10, 0x14 (outside the line) and missing 0x00, 0x04 (in the line) — a broken fill. If the DMA used WRAP4 for the linear copy, the 4 words would wrap at the aligned boundary, scrambling the linear order. So each must use its correct type: WRAP4 for the cache fill, INCR4 for the linear copy.
  • Larger lines. If the CPU instead had 8-word lines, it would use WRAP8 (chapter 8.5) for fills; 16-word lines would use WRAP16. The WRAP length matches the line size. The 4-beat WRAP4 is for 4-word lines specifically.

The example shows the 4-beat split: WRAP4 for the 4-word cache line fill (critical-word-first, wrapping within the aligned line, reducing miss latency), and INCR4 for a known 4-beat linear block (the structure copy). The memory prefetches the exact line (fixed count), and swapping the types would break both accesses. WRAP4's wrapping is precisely what the cache fill needs.

8. Common Mistakes

9. Interview Insight

WRAP4/INCR4 are a common interview topic — the wrap mechanics and the cache-line connection are the test.

A summary card contrasting INCR4 (linear) and WRAP4 (wrapping within the aligned block), with the cache-line use case and the wrap-the-low-bits mechanic.
Figure 4 — a strong answer in one card: INCR4 and WRAP4 are both fixed 4-beat bursts; INCR4 increments linearly (may cross the aligned boundary), while WRAP4 wraps within the aligned block of size 4 × beat-size (the four beats stay in one block). WRAP4 serves 4-word cache line fills (critical-word-first); INCR4 serves a known 4-beat linear block. The senior point: WRAP wraps the lower address bits at the 4×size boundary while the upper bits stay fixed.

The answer that lands explains the wrap concretely and connects it to caches: "INCR4 and WRAP4 are both 4-beat fixed-length bursts. INCR4 increments linearly — each beat is the previous plus the beat size — and can cross an aligned boundary. WRAP4 also increments, but it wraps within the aligned block of size 4 times the beat size: when the address reaches the block boundary, it wraps back to the block's start, so all four beats stay inside one aligned block. Concretely, a WRAP4 of words from 0x08 goes 0x08, 0x0C, then wraps to 0x00, 0x04 — staying in the 16-byte block — while INCR4 would go 0x08, 0x0C, 0x10, 0x14, crossing the boundary. WRAP4 exists for 4-word cache line fills: it can start at the critical (missed) word and wrap to cover the rest of the line, delivering critical-word-first within the aligned line — which INCR can't do because it increments away from the earlier words. Mechanically, WRAP wraps the lower address bits at the 4×size boundary while the upper bits stay fixed." The concrete wrap example, the critical-word-first cache connection, and the wrap-the-low-bits mechanic are the senior signals.

10. Practice Challenge

Reason from the 4-beat bursts.

  1. Contrast the patterns. Give the address sequence for an INCR4 and a WRAP4 of words starting at 0x08.
  2. The wrap math. Explain how WRAP4 wraps (which bits, what boundary) and what determines the block size.
  3. Read the waveform. From Figure 3, identify where the WRAP4 wraps and why it stays in the block.
  4. Cache fill. Explain why WRAP4 serves a 4-word cache line fill and INCR4 can't.
  5. Choose the type. Given a 4-word cache fill and a 4-word linear structure copy, state which uses WRAP4 and which INCR4.

11. Key Takeaways

  • INCR4 and WRAP4 are both 4-beat fixed-length bursts — the count (4) is declared via HBURST, enabling precise memory prefetch.
  • INCR4 increments linearly (can cross the aligned boundary); WRAP4 wraps within the aligned block of size 4 × beat-size (the four beats stay in one block).
  • Concretely (words from 0x08): INCR4 → 0x08, 0x0C, 0x10, 0x14; WRAP4 → 0x08, 0x0C, 0x00, 0x04 (wraps at 0x10 back to 0x00).
  • WRAP4 wraps the lower address bits (within the block) while the upper bits (block base) stay fixed — the boundary matches cache line alignment by construction.
  • WRAP4 serves 4-word cache line fills, critical-word-first — start at the critical word, wrap to cover the line — reducing CPU miss latency. INCR4 can't (it increments away from earlier words).
  • Match the type to the pattern: cache fill → WRAP4 (wrap within the line), known linear 4-beat block → INCR4 (march straight). The wrap is required for critical-word-first.

12. What Comes Next

You now understand the 4-beat bursts and the wrap mechanics. The next chapters scale to longer bursts:

  • 8.5 — WRAP8 & INCR8 Bursts (coming next) — the 8-beat fixed-length bursts (larger cache lines, longer blocks).
  • 8.6 — WRAP16 & INCR16 Bursts (coming soon) — the 16-beat bursts.

To revisit the burst concept, see Burst Overview; for the undefined-length type, INCR (Undefined-Length) Bursts. For the per-beat address progression, the detailed burst-address-calculation and boundary-wrapping chapters come later in this module. For the HBURST signal, see HBURST. For the broader protocol map, see the AMBA family overview.