Resources

The whole learning graph, one place to start.

Every hand-authored track VLSI Mentor publishes — HDLs, verification, on-chip protocols, high-speed interconnect, EDA scripting, and timed practice. Pick a thread and follow it lesson by lesson.

Core HDL

Hardware description and reusable RTL architecture — the languages and structures every design starts from.

Verilog

SystemVerilog

VHDL

RTL Design Patterns

Reusable RTL structures — FSMs, FIFOs, pipelines, handshakes, arbiters, and CDC.

Verification

Methodology, register modeling, and signoff reasoning — how a design is proven correct before tape-out.

UVM

UVM RAL

Gate Level Simulation (GLS)

Netlist simulation, SDF timing, X-propagation, and signoff debug.

Design for Testability (DFT)

Scan, ATPG, test modes, coverage, and manufacturing-test reasoning.

Protocols

On-chip and serial interconnect — the AMBA fabric and buses that move data across a system-on-chip.

AMBA APB

AMBA AHB

AMBA AXI

AMBA CHI

Wishbone

UART

SPI

I²C

USB

High-Speed & System

High-bandwidth links and memory — the interconnect that ties chips, packages, and boards together.

PCIe

CXL

UCIe

Ethernet

DDR

Programming & Automation

The scripting, shell, and build tooling that every semiconductor engineer eventually owns.

Linux Bash Shell

Tcl

Python

Makefile

awk

sed

Perl

C Programming

C++ Programming

MCQ Practice

Timed, topic-tagged papers with an explanation on every answer. A free sample per subject — try before you unlock the pack.

Engineering Journal

Short, timely writing on RTL, verification, and protocols — real bugs, methodology shifts, and mental models.

Read the journal