Practice, watch, and build the muscle memory.
Two formats for two different jobs — topic-tagged MCQ practice tightens recall, video lessons give you a working example to copy. All taught by engineers who do this work for a living.
MCQ Assessments
Timed, topic-tagged assessment papers with per-topic analysis and tutorial recommendations. Verilog HDL available now, more subjects on the way.
Open assessmentsVideo Courses
Lab-paced video walkthroughs — write the RTL, set up the testbench, run the regression.
Watch the seriesAssessment packs
Verilog HDL Assessment Pack
- 100+ Questions
- Topic Analysis
- Tutorial Recommendations
Full catalogue
Industry-grade training across the core languages and methodologies used by modern RTL and verification teams.
Verilog
Build a working foundation in Verilog — modeling, simulation, and synthesizable RTL.
SystemVerilog
OOP, interfaces, randomization, functional coverage, and assertion-based verification.
UVM
Universal Verification Methodology — agents, environments, sequences, and reusable VIP architecture.
Digital Electronics
Boolean algebra, combinational and sequential logic, timing, and the silicon-to-RTL bridge.
C / C++
Practical C and modern C++ used in DPI, reference models, and EDA tooling pipelines.
Python
Automation for waveform parsing, log analysis, coverage merging, and regression dashboards.
Perl
Production Perl for EDA flows — log scraping, report generation, and tool wrappers.
TCL
TCL for synthesis, P&R, and verification tool scripting across the EDA toolchain.
Linux
The Linux engineer mindset — filesystems, processes, networking, and the dev workflow.
Shell Scripting
Bash and POSIX scripting for build flows, regression runners, and CI orchestration.