WRAP16 & INCR16 Bursts

Chapters 8.4–8.5 covered the 4- and 8-beat bursts. This chapter covers the 16-beat pair — INCR16 and WRAP16, the largest fixed-length bursts. They are the same patterns scaled once more: INCR16 is sixteen linear beats; WRAP16 wraps within the aligned block of size 16 × beat-size (64 bytes for words). They serve 16-word (64-byte) cache line fills and large block transfers. As the longest fixed bursts, they sit at the high end of the throughput-vs-latency spectrum (chapter 8.5): they amortize overhead the most and give the highest throughput, but they hold the bus the longest — so they suit throughput-dominated traffic (large DMA, big cache lines) and are a poor fit for latency-sensitive, heavily-contended buses. Since the mechanics are now familiar, this chapter focuses on when the 16-beat length is worth its bus-hold.

1. What Is It?

INCR16 and WRAP16 are the 16-beat fixed-length bursts — the largest fixed bursts:

• INCR16 — sixteen beats, address incrementing linearly (each beat = previous + beat size). Marches through sixteen consecutive locations.
• WRAP16 — sixteen beats, address incrementing but wrapping within the aligned block of size 16 × beat-size (64 bytes for words). The sixteen beats stay inside one aligned 64-byte block.

The mechanics are identical to WRAP4/8, scaled to 16 beats: the block (and wrap boundary) is now 16 × beat-size. WRAP16 wraps the lower address bits within the aligned 64-byte block (for words); INCR16 increments linearly. Both declare exactly 16 beats via HBURST, giving precise 16-beat prefetch. So WRAP16/INCR16 are simply the longest instance of the fixed-length pattern — the wrap-the-low-bits, stay-in-the-aligned-block behavior carries over with the largest block. WRAP16 serves 16-word (64-byte) cache lines, a common large-line size.

2. Why Does It Exist? (And when to use 16 beats?)

The 16-beat bursts exist for the largest known blocks — 16-word (64-byte) cache lines and big DMA chunks — and the question this chapter answers is when the 16-beat length (with its maximum amortization but longest bus-hold) is the right choice.

The existence rationale completes the fixed-length series: WRAP4 for 4-word lines, WRAP8 for 8-word lines, WRAP16 for 16-word (64-byte) lines — a common large cache line size. So WRAP16 exists to fill 64-byte lines, the largest common line size, critical-word-first. INCR16 serves large known linear blocks (big DMA chunks). The fixed 16-beat count gives precise 16-beat prefetch. So the 16-beat types are the series' top end, for the largest known blocks.

The when-to-use-16 question is the throughput-vs-latency tradeoff (chapter 8.5) at its extreme. 16-beat bursts amortize overhead the most (over 16 beats) and let memory stream the most per row-open — maximum throughput. But they hold the bus/path for 16 beats — the longest bus-hold, making other masters wait longest (worst latency/fairness). So 16 beats is worth it precisely when throughput dominates and the latency cost is acceptable.

So 16 beats is the right choice when bandwidth matters most: large DMA transfers where throughput is the goal, 64-byte cache lines (exploiting spatial locality and amortizing the fill), systems with few contending masters, or interconnects that give separate paths (so one master's long burst doesn't block others). It's the wrong choice for latency-sensitive, heavily-contended single shared buses, where a 16-beat burst would make other masters wait too long — there, shorter bursts (4/8-beat) are better. So the 16-beat length exists for the throughput end, and the architect uses it when throughput justifies the bus-hold. This completes the spectrum: 4-beat (latency), 8-beat (balance), 16-beat (throughput).

3. Mental Model

Model the 16-beat burst as filling a large tanker truck in one go versus making several smaller deliveries — one big fill is most efficient per trip, but the loading dock is occupied for a long time, blocking everyone else.

Delivering fuel (moving data), you can use a small van (4-beat), a medium truck (8-beat), or a large tanker (16-beat). The large tanker (16-beat burst) carries the most per trip — most efficient, fewest trips, best throughput. But filling it takes the longest, and while it's at the loading dock (holding the bus), no one else can use the dock — everyone waits a long time. So the tanker is great when you're the main user and throughput is what matters (few others need the dock, or there are separate docks — separate interconnect paths). But on a busy shared dock with many trucks waiting (a contended multi-master bus), parking a tanker there blocks everyone too long — you'd use smaller trucks (shorter bursts) so the dock frees up frequently. The tanker's efficiency is real, but so is the cost of monopolizing the dock.

This captures the 16-beat choice: the large tanker = the 16-beat burst (most per trip, best throughput); occupying the dock long = the longest bus-hold; fine when you're the main user / separate docks = throughput-dominated or few-contender / separate-path systems; bad on a busy shared dock = latency-sensitive contended buses. Biggest is most efficient but monopolizes the shared resource longest.

Watch a WRAP16 wrap (showing the wrap point):

The model's lesson: WRAP16 is the large tanker — sixteen beats wrapping within the aligned 64-byte block, the most efficient per burst but the longest bus-hold. In the waveform, the address wraps from 0x3C back to 0x00 at the 64-byte boundary, keeping all sixteen beats in the aligned line. Maximum amortization, longest occupation of the bus.

4. Real Hardware Perspective

In hardware, WRAP16/INCR16 are the fixed-length pattern with the largest boundary (16 × beat-size) — and their longest bus-hold is what makes interconnect burst-length limits and 64-byte cache lines the relevant design context.

The address generation scales once more: for WRAP16 of words, the block is 64 bytes (lower 6 bits index within it), so the manager increments the low 6 bits mod 64 (wrapping at 64), keeping the upper bits fixed — versus WRAP8's low-5-bits-mod-32 and WRAP4's low-4-bits-mod-16. INCR16 is a plain increment for 16 beats. So again, only the number of wrapping low bits (6) and the beat count (16) change; the wrap mechanic is identical. A manager supporting all WRAP lengths parameterizes the boundary from HBURST/HSIZE.

The 64-byte cache line is the hardware context for WRAP16. Many modern CPUs use 64-byte cache lines (16 words), filled with WRAP16, critical-word-first. So WRAP16 is tied to the 64-byte line size — a common choice for larger caches that exploit more spatial locality. The longer line (more spatial locality, fewer misses, better fill amortization) trades against longer fill latency and longer bus-hold — and 64-byte lines are common in higher-performance systems where the locality benefit wins. So WRAP16 reflects the 64-byte-line design choice.

The interconnect's burst-length limits are most relevant for 16-beat bursts (and unbounded INCR). Because a 16-beat burst holds the path longest, interconnects with fairness requirements may limit how long a single burst can hold a path — potentially requiring long bursts to yield, or arbitrating between them (chapters 8.5, 12.x). So the system's fairness mechanisms are most exercised by the longest bursts. In a heavily-contended interconnect, 16-beat bursts may be discouraged or bounded to avoid starving others; in a system with separate paths (a bus matrix giving each master its own route), a 16-beat burst on one path doesn't block others, so it's fine. So the interconnect topology determines whether 16-beat bursts are acceptable — separate paths make them fine, a single shared path makes their bus-hold costly.

A hardware note on memory efficiency: a 16-beat fixed burst lets the memory controller stream the most from an opened row before doing anything else — the best row-open amortization of the fixed types. So for DRAM, longer bursts (16-beat) extract the most bandwidth per row activation. This is why throughput-oriented systems favor longer bursts at the memory level: more beats per expensive row-open. The 16-beat burst maximizes this, which is its core throughput advantage in hardware.

5. System Architecture Perspective

At the system level, WRAP16/INCR16 are the throughput-end bursts — used where bandwidth is paramount (large DMA, 64-byte cache lines, high-performance datapaths) — and their suitability depends heavily on the interconnect topology and the system's latency tolerance.

The throughput-end role is clear: 16-beat bursts maximize amortization and memory streaming, so they're used where throughput is the priority. Large DMA transfers (moving big buffers fast), 64-byte cache lines (high-performance CPUs exploiting spatial locality), and bulk datapaths (graphics, networking) favor 16-beat bursts for their bandwidth. So in throughput-dominated subsystems, WRAP16/INCR16 are the natural choice. They complete the spectrum's high end: where maximum bandwidth matters and the latency cost is tolerable, 16-beat bursts deliver.

The interconnect topology is the key determinant of whether 16-beat bursts are appropriate. On a single shared bus (one path, multiple masters contending), a 16-beat burst blocks all other masters for 16 beats — costly for latency. But on a bus matrix / multi-layer interconnect (chapters 12.x) where each master has its own path to the subordinates, one master's 16-beat burst on its path doesn't block another master on a different path — so the bus-hold cost is contained. So 16-beat bursts are much more acceptable in matrix interconnects (separate paths) than on a single shared bus. This is why high-performance systems (which use matrix interconnects and want throughput) can freely use long bursts: the topology removes the contention cost. So the architecture (single bus vs matrix) shapes the burst-length choice — matrix interconnects enable the throughput-end bursts.

The latency tolerance of the system is the other factor. Real-time and latency-sensitive systems (where masters need quick bus access) avoid long bursts to keep the bus responsive; throughput-oriented systems (where sustained bandwidth matters more than individual access latency) favor them. So the 16-beat choice reflects the system's priorities: bandwidth-first → 16-beat, latency-first → 4/8-beat. Most systems mix — using long bursts for the throughput datapath (DMA, cache fills via the matrix) and shorter accesses for latency-sensitive control. So the burst-length spectrum (4/8/16) maps onto the system's mix of throughput and latency needs, with 16-beat serving the throughput-critical, topology-permitting cases. This completes the burst module's central theme: match the burst length to the traffic's priority and the interconnect's topology.

6. Engineering Tradeoffs

The 16-beat bursts sit at the throughput end of the tradeoff.

• 16 beats vs 8 vs 4. 16-beat bursts amortize overhead most and stream most per row-open (highest throughput) but hold the bus longest (worst latency/fairness). The series 4/8/16 trades increasing throughput for increasing bus-hold; 16 is the throughput extreme.
• 64-byte lines (WRAP16) vs smaller. 64-byte cache lines exploit the most spatial locality and amortize fills best, at the cost of longer fill latency, more bandwidth/capacity on unused words, and the longest fill bus-hold. Higher-performance systems favor them; latency- or capacity-constrained ones use smaller lines.
• Single shared bus vs matrix interconnect. On a single shared bus, 16-beat bursts are costly (block others longest); on a matrix (separate paths), they're fine (don't block other paths). The topology determines whether the throughput-end bursts are acceptable.
• Throughput-first vs latency-first systems. Throughput-oriented systems favor 16-beat bursts; latency-sensitive ones avoid them. The choice reflects the system's priority.

The throughline: WRAP16/INCR16 are the largest fixed bursts — the throughput end of the spectrum. They maximize amortization and bandwidth (best row-open amortization, fewest arbitrations) at the cost of the longest bus-hold. They suit throughput-dominated traffic (large DMA, 64-byte cache lines) and are enabled by matrix interconnects (separate paths) that remove the contention cost — but are a poor fit for latency-sensitive, heavily-contended single shared buses. They complete the burst-length spectrum: 4 (latency), 8 (balance), 16 (throughput).

7. Industry Example

Trace the 16-beat bursts in a high-performance system.

A high-performance SoC has a CPU with 64-byte cache lines, a DMA engine moving large buffers, and a matrix interconnect giving masters separate paths to memory.

• A cache miss — WRAP16 fill. The CPU (64-byte/16-word lines) misses on a load. It issues a WRAP16 burst from the critical word, wrapping within the aligned 64-byte line — fetching all sixteen words critical-word-first. The 64-byte line exploits spatial locality (likely fewer future misses), and WRAP16 fills it efficiently with the best row-open amortization. The CPU resumes on the critical word while the line fills.
• A large DMA transfer — INCR16 chunks. The DMA engine moves a large buffer using INCR16 bursts (16-beat chunks) for maximum throughput — amortizing overhead over 16 beats and streaming the most per row-open. The big chunks move the buffer fast.
• The matrix interconnect makes it work. Crucially, the DMA's 16-beat bursts run on its own path through the matrix interconnect, and the CPU's cache fills run on theirs — so the DMA's long bursts don't block the CPU. The separate paths remove the contention cost of the long bursts. This is what lets the system use 16-beat bursts freely: the topology (matrix) means one master's long burst doesn't starve another.
• Why this works here. This system is throughput-oriented (high bandwidth for CPU caches and DMA) and uses a matrix interconnect (separate paths). Both conditions favor 16-beat bursts: throughput is the priority, and the topology absorbs the bus-hold. So WRAP16/INCR16 are the right choice — maximum bandwidth, with the matrix preventing contention.
• Contrast: a simple shared-bus system. A simpler system with a single shared AHB and several latency-sensitive masters would avoid 16-beat bursts — a 16-beat burst would block the other masters too long. It would use shorter bursts (4/8-beat) and smaller cache lines, accepting less throughput for better responsiveness. So the same burst length is right for the matrix/throughput system and wrong for the shared-bus/latency system.

The example shows the 16-beat bursts in their proper context: a throughput-oriented, matrix-interconnect system where WRAP16 fills 64-byte cache lines and INCR16 moves large DMA buffers, with the separate paths removing the contention cost. The contrast (a shared-bus latency-sensitive system avoiding them) shows the context-dependence: 16-beat bursts deliver maximum throughput where the topology and priorities support them.

8. Common Mistakes

9. Interview Insight

WRAP16/INCR16 are usually tested as the throughput-end of the burst spectrum — knowing when 16-beat is appropriate (and when not) is the signal.

The answer that lands frames 16-beat as the throughput extreme with context-dependence: "INCR16 and WRAP16 are the largest fixed-length bursts — 16 beats, the same patterns scaled, with a 64-byte block for words. INCR16 marches through 16 consecutive locations; WRAP16 wraps within the aligned 64-byte block, serving 16-word (64-byte) cache line fills. They're at the throughput end of the spectrum: they amortize overhead the most and stream the most per memory row-open, giving the highest throughput — but they hold the bus the longest, so they make other masters wait longest. That means they're appropriate when throughput dominates and the context can absorb the bus-hold: large DMA transfers, 64-byte cache lines, and especially matrix interconnects where each master has its own path so a long burst on one path doesn't block others. They're a poor fit for a single shared bus with many latency-sensitive masters — there you'd use shorter 4/8-beat bursts. So 16-beat completes the spectrum: 4 for latency, 8 for balance, 16 for throughput." The throughput-end framing, the context-dependence (matrix interconnect, throughput-first), and the completed spectrum are the senior signals.

10. Practice Challenge

Reason from the 16-beat bursts and the spectrum.

1. Scale the pattern. Give the WRAP16 block size for words and which address bits wrap.
2. Read the waveform. From Figure 3, identify the WRAP16 wrap point and confirm it stays in the block.
3. When to use. State the contexts where 16-beat bursts are appropriate and where they're not.
4. Topology. Explain why a matrix interconnect makes 16-beat bursts acceptable.
5. The spectrum. Place 4/8/16-beat bursts on the throughput-vs-latency spectrum.

11. Key Takeaways

• INCR16 and WRAP16 are the largest fixed-length bursts (16 beats) — the WRAP4/8 patterns scaled, with the biggest block (16 × beat-size = 64 bytes for words).
• WRAP16 serves 16-word (64-byte) cache line fills, critical-word-first; INCR16 serves large known linear blocks. Same wrap mechanic, biggest boundary.
• They're the throughput end of the spectrum — maximum amortization and bandwidth (best row-open amortization) but the longest bus-hold.
• Appropriate when throughput dominates and the context absorbs the bus-hold — large DMA, 64-byte cache lines, few contenders, or a matrix interconnect (separate paths); a poor fit for latency-sensitive contended shared buses.
• Interconnect topology is decisive — a matrix interconnect (separate paths) makes 16-beat bursts fine; a single shared bus makes their bus-hold costly.
• They complete the burst-length spectrum: 4-beat (latency), 8-beat (balance), 16-beat (throughput) — choose the point matching the system's priorities and topology.

12. What Comes Next

You now understand all the fixed-length bursts. The next chapters cover the address math and boundary behavior in depth:

• 8.7 — Burst Address Calculation (coming next) — deriving per-beat addresses for INCR and WRAP bursts with the formulas and worked examples.
• 8.8 — Boundary Wrapping (coming soon) — the wrap boundary math and why WRAP bursts exist.

To revisit the smaller fixed bursts, see WRAP4 & INCR4 Bursts and WRAP8 & INCR8 Bursts; for the undefined-length type, INCR (Undefined-Length) Bursts; for the overview, Burst Overview. For the HBURST signal, see HBURST. For the broader protocol map, see the AMBA family overview.