HBURST

This chapter covers HBURST, the burst-type signal — how many beats a burst has and what address pattern they follow. You met bursts conceptually in chapter 2.6 and saw NONSEQ/SEQ mark their beats in 3.3; here we give the eight HBURST encodings their exact meaning, distinguish the INCR (incrementing) and WRAP (wrapping) families, explain why WRAP exists, and pin down the 1 KB boundary rule that bounds every burst. HBURST is where a burst's shape is declared, and it works hand-in-hand with HSIZE (beat width) and HTRANS (per-beat type).

1. What Is It?

HBURST is a 3-bit address-phase signal, driven by the manager on the first beat of a burst, declaring the burst's length and address pattern. Its eight values fall into two families plus the single case:

• 000 — SINGLE: one beat, not a burst.
• 001 — INCR: an incrementing burst of unspecified length — the address increments each beat, and the burst ends when the manager stops issuing SEQ beats.
• 011 — INCR4, 101 — INCR8, 111 — INCR16: fixed-length incrementing bursts of 4, 8, or 16 beats.
• 010 — WRAP4, 100 — WRAP8, 110 — WRAP16: fixed-length wrapping bursts of 4, 8, or 16 beats — the address increments but wraps at an aligned boundary so the beats stay within one aligned block.

The structure to hold: there is SINGLE (no burst), one unspecified-length incrementing burst (INCR), and three fixed lengths (4, 8, 16) each in an INCR and a WRAP flavour. INCR versus WRAP is purely the address pattern — increment forever versus increment-and-wrap-in-a-block — for the same number of beats.

2. Why Does It Exist?

HBURST exists to let a manager declare the shape of a burst up front so the subordinate and interconnect can optimize for it — and the two families exist because two different access patterns dominate real traffic.

Recall from chapter 2.6 that a burst's power is foreknowledge: declaring "a 4-beat incrementing burst is starting" lets the subordinate prefetch and prepare. HBURST is that declaration. Without it, the subordinate would see only individual beats (via HTRANS NONSEQ/SEQ) without knowing the burst's length or pattern, so it could not look ahead efficiently. HBURST gives the subordinate the burst's shape in one signal on the first beat.

Why the INCR family. Most bulk movement is sequential: a DMA copying a buffer, a processor streaming through memory. The address simply marches forward by the beat size. INCR (and its fixed-length forms INCR4/8/16) expresses exactly this — increment each beat. The fixed-length forms tell the subordinate precisely how many beats are coming (best foreknowledge); the unspecified-length INCR is for when the manager does not know the length in advance and ends the burst when done.

Why the WRAP family. Cache-line fills have a special pattern. When a processor misses on a particular word, the memory system wants to deliver that word first (the critical word the CPU is stalled on) and then fill the rest of the cache line. The address therefore starts at the critical word, increments, and wraps at the line boundary to fill the earlier words of the line — staying within the aligned line. WRAP4/8/16 express exactly this wrapping pattern. WRAP exists specifically because cache-line-fill-with-critical-word-first is a common, important access pattern that plain incrementing cannot express.

So HBURST exists to declare burst shape for optimization, and it offers two families because sequential bulk movement (INCR) and critical-word-first cache fills (WRAP) are the two dominant burst patterns in real systems. The encoding covers both, at fixed lengths (maximum foreknowledge) and an unspecified incrementing length (flexibility).

3. Mental Model

Model HBURST as the route plan handed to the delivery driver at the start of a run.

When a burst begins (the NONSEQ first beat), the manager hands over a route plan — HBURST — that says how the run will go:

• SINGLE = "one stop, that's it."
• INCRn = "n stops, each at the next address up the street" — a straight march.
• INCR (unspecified) = "keep going up the street until I say stop" — a straight march of unknown length.
• WRAPn = "n stops within this block, starting where I said, and circling back to the start of the block" — a loop within an aligned neighbourhood, used when you want to start at a particular house (the critical word) but cover the whole block.

The dispatcher (subordinate) reads the route plan once and prepares for the whole run — prefetching the stops it knows are coming. The plan is declared at the start and the beats then follow it, marked SEQ by HTRANS.

Watch an INCR4 burst at signal level:

The model's lesson: HBURST is the route plan, declared once at the start, and the SEQ beats execute it. INCR marches straight; WRAP loops within an aligned block. The subordinate, having read the plan, prepares for the whole run.

4. Real Hardware Perspective

In hardware, HBURST is read on the burst's first beat and drives both the manager's address generation and the subordinate's prefetch — and it carries the important 1 KB boundary constraint.

The manager's address generation follows HBURST: for INCR, a simple increment by the beat size each beat; for WRAP, an increment that wraps at the aligned boundary determined by the burst length and beat size (a 4-beat word WRAP wraps within a 16-byte block, an 8-beat within 32 bytes, etc.). The wrap boundary is exactly the burst's total size, aligned — which is why WRAP bursts are inherently aligned to their length. The subordinate, reading HBURST on the first beat, knows the pattern and length and can prefetch the beats it knows are coming.

The 1 KB boundary rule is a key hardware constraint: a burst must not cross a 1 KB address boundary. The reason is that the address decode (which subordinate owns the address) could change across a 1 KB boundary — a burst that crossed it might run off the end of one subordinate's region into another's, which the single declared burst cannot handle. So managers must size and align bursts (especially long INCR bursts) so they stay within a 1 KB-aligned region; a burst approaching the boundary must be broken into separate bursts. This rule ties HBURST to the address map's granularity and is a classic thing to get right in address generation.

There is also the unspecified-length INCR mechanic: unlike the fixed-length bursts, INCR does not tell the subordinate how many beats are coming. The manager simply keeps issuing SEQ beats and ends the burst by no longer issuing SEQ (moving to IDLE, or to a NONSEQ for a new burst). This gives flexibility (the manager need not know the length up front) at the cost of less foreknowledge for the subordinate, which cannot know in advance how far to prefetch. Fixed-length bursts trade that flexibility for maximal subordinate optimization.

5. System Architecture Perspective

At the system level, HBURST is how masters express their access patterns to the memory system, and the choice of burst type and length is a real performance lever.

Different masters use different HBURST types reflecting their access patterns. A processor cache uses WRAP bursts for line fills (critical word first) and may use INCR for write-backs. A DMA engine uses INCR bursts (often fixed-length INCR4/8/16, or unspecified INCR) for bulk sequential movement. So HBURST is the bus-level fingerprint of what a master is doing, and a memory controller can even use the burst type as a hint about the access's nature (a WRAP suggests a cache fill, an INCR a stream). The system's masters and their burst types together shape the traffic the memory subsystem sees.

Burst length is a performance and fairness lever, as established in chapter 2.6: longer bursts (INCR16, or long unspecified INCR) amortize arbitration and sustain bandwidth but hold the bus longer, hurting other masters' latency; shorter bursts are fairer but less efficient. The 1 KB boundary rule also bounds how long a single burst can be in practice. So a system tunes its masters' burst lengths — and the arbiter's handling of them — to balance throughput against latency, and HBURST is where each master's choice is expressed.

The WRAP-for-cache-fills pattern is a system-level optimization worth appreciating: by using WRAP, a cache fill gets the critical word to the stalled processor first, reducing the processor's stall time, while the rest of the line fills behind it. This is a measurable latency win that depends entirely on HBURST's WRAP family existing. A system whose caches used plain INCR fills would deliver the critical word later (after the earlier words of the line), increasing stall time. So HBURST's WRAP encodings are not academic — they directly reduce processor stall latency in real chips.

6. Engineering Tradeoffs

HBURST's choices are about foreknowledge, flexibility, and access-pattern fit.

• Fixed-length vs unspecified-length bursts. Fixed-length (INCR4/8/16, WRAP4/8/16) give the subordinate maximal foreknowledge (it knows exactly how many beats) for best prefetch, but commit the manager to that length. Unspecified-length INCR is flexible (the manager ends it when done) but gives less foreknowledge. The trade is subordinate optimization versus manager flexibility.
• WRAP vs INCR for the same data. WRAP serves critical-word-first cache fills (lower processor stall), but only makes sense for aligned-block access patterns; INCR serves general sequential movement and is simpler to generate. Using WRAP where INCR fits (or vice versa) wastes the benefit. The trade is access-pattern fit — pick the family that matches what the master is actually doing.
• Long bursts vs the 1 KB boundary and latency. Longer bursts amortize overhead and sustain bandwidth, but they hold the bus longer (hurting others' latency) and must not cross a 1 KB boundary (bounding their length and forcing splits). The trade is throughput versus latency and the boundary constraint, resolved by bounding and aligning burst lengths.
• Declaring shape up front vs adapting. HBURST commits the burst's shape on the first beat, enabling optimization but preventing mid-burst changes (you cannot turn an INCR4 into an INCR8 partway). This early commitment is what makes the foreknowledge reliable, so it is the right trade for a pipelined, optimization-friendly bus — at the cost of flexibility to change the burst once started.

The through-line: HBURST trades commitment for foreknowledge. Declaring the burst's shape up front — and choosing the family and length that match the access pattern — lets the subordinate optimize, at the cost of being locked into that shape and bounded by the 1 KB rule. Matching HBURST to the master's actual access pattern (WRAP for cache fills, INCR for streams, appropriate length for the throughput/latency balance) is the engineering skill.

7. Industry Example

Trace HBURST across a cache fill and a DMA stream on a real system.

• A cache-line fill (WRAP). A processor misses in its data cache on a word partway through a line. To fill the line, it issues a WRAP burst (say WRAP8 for an 8-word line) starting at the critical word — the one it missed on. The address increments from the critical word and wraps at the aligned line boundary, covering the whole line but delivering the critical word first. The processor gets the data it stalled on as early as possible and can resume, while the rest of the line fills behind it. HBURST = WRAP8 is what expresses this critical-word-first pattern; the latency win is real and direct.
• A DMA block copy (INCR). A DMA engine copies a large buffer. It issues INCR bursts — perhaps fixed-length INCR16 for maximal foreknowledge and efficiency, or unspecified-length INCR if the length is dynamic — with the address marching forward by the beat size. The memory controller, seeing INCR16, prefetches the run and streams it efficiently. For a buffer larger than 1 KB, the DMA must break the transfer into multiple bursts so that no single burst crosses a 1 KB boundary — so a 4 KB copy becomes a sequence of bursts, each within a 1 KB-aligned region.
• The boundary in action. Suppose the DMA naively issued one enormous INCR burst across a 4 KB buffer. It would cross multiple 1 KB boundaries, violating the rule, and could run past the intended subordinate's region with undefined results. The correct DMA address generator detects the boundaries and splits the transfer — a concrete, everyday consequence of the 1 KB rule that DMA designers must handle.
• A single access (SINGLE). A processor's lone byte write to a peripheral register uses HBURST = SINGLE — one beat, no burst. Not every access is a burst; SINGLE is the common case for incidental, one-off accesses.

Every burst on the bus declares its shape via HBURST on the first beat: WRAP for cache fills (critical word first), INCR for streams, SINGLE for one-offs — and all bounded by the 1 KB boundary rule. The cache's WRAP fills and the DMA's boundary-respecting INCR bursts are HBURST doing its everyday work.

8. Common Mistakes

9. Interview Insight

HBURST questions test the INCR/WRAP distinction, the reason for WRAP, and the 1 KB boundary rule.

The answer that lands gives the families, the WRAP rationale, and the boundary rule: "HBURST is 3 bits: SINGLE for one beat, INCR for an unspecified-length incrementing burst, and fixed-length WRAP4/INCR4 through WRAP16/INCR16. INCR just increments the address; WRAP increments then wraps at the aligned boundary, which exists for critical-word-first cache-line fills. And a key rule: a burst must not cross a 1 KB address boundary, so long transfers are split." The WRAP rationale and the 1 KB rule are the senior signals.

10. Practice Challenge

Reason from the families and the 1 KB rule.

1. Organize the encoding. List the eight HBURST values grouped into SINGLE, the INCR family, and the WRAP family.
2. Trace the addresses. For INCR4 and WRAP4 word bursts starting at 0x4, write the four addresses each visits.
3. Justify WRAP. In two sentences, explain why a cache uses WRAP for line fills and the latency benefit.
4. Apply the boundary rule. A DMA must copy 4 KB starting at a 1 KB-aligned address. Explain how it must structure the bursts and why.
5. Diagnose the hang. A DMA intermittently corrupts large transfers. Explain how a burst crossing a 1 KB boundary could cause it and why it is intermittent.

11. Key Takeaways

• HBURST is a 3-bit burst-type signal: SINGLE (one beat), INCR (unspecified-length incrementing), and fixed-length INCR4/8/16 and WRAP4/8/16.
• INCR vs WRAP is the address pattern, not the length — INCRn and WRAPn both have n beats; INCR increments, WRAP increments-and-wraps at the aligned boundary.
• WRAP exists for critical-word-first cache-line fills — it delivers the missed word first and wraps to fill the rest of the aligned line, reducing processor stall latency.
• A burst must not cross a 1 KB address boundary — because decode can change at region boundaries, so long transfers are split into multiple bursts each within a 1 KB-aligned region.
• HBURST is declared on the first (NONSEQ) beat and the SEQ beats follow the declared pattern; it works with HSIZE (beat width) and HTRANS (per-beat type).
• Burst type and length are a performance lever — WRAP for cache fills, INCR for streams, length balancing throughput against latency and bounded by the 1 KB rule.

12. What Comes Next

You now know how an access's address, direction, type, size, and burst shape are all encoded. The remaining address-phase signal carries the access's attributes, then the module turns to the data and response signals:

• 3.6 — HPROT (coming next) — the protection and attribute hints (privilege, cacheability, bufferability) that accompany the access.
• 3.7 — HWDATA & HRDATA (coming soon) — the write- and read-data buses, in detail.

To revisit how HBURST's beats stream and pipeline, see Single Transfer vs Burst Transfer, HTRANS, and HSIZE. For the broader protocol map, see the AMBA family overview.