Verilog tutorials & labs.
Digital design fundamentals, combinational logic, sequential circuits, counters, shift registers, and FSMs — taught through synthesizable RTL examples.
Tutorials
Learn Verilog from beginner to advanced through structured tutorials — free.
Labs
Premium hands-on labs — explained code, self-checking testbenches, and 2 portfolio projects.
What Verilog is
Verilog is a hardware description language: you write text, and a synthesis tool turns it into gates and flip-flops. That single sentence hides the thing that trips up almost everyone arriving from software — a Verilog module is not a program that runs top to bottom. Every continuous assignment and every always block is a piece of hardware that exists simultaneously, reacting whenever its inputs change. Standardised as IEEE 1364 and later folded into IEEE 1800, Verilog remains the language most RTL is written in, and the foundation SystemVerilog extends rather than replaces.
Why it exists
Before HDLs, digital design meant schematics — every gate placed by hand, every change re-drawn. Verilog let engineers describe behaviour at register-transfer level and hand the gate-level detail to a synthesis tool, which is what made designs of millions of gates tractable at all. The trade is that the tool now decides your hardware from your description, so the quality of what you get depends entirely on how precisely you said what you meant.
The part engineers get wrong
The most expensive misconception is that statement order inside a module implies execution order. It does not: separate always blocks are concurrent hardware. But order does matter *inside* one block, and that is exactly where blocking (=) and non-blocking (<=) assignments diverge. Using = in a clocked block makes one flip-flop's new value visible to the next statement in the same clock edge — modelling a shift register as a single wide register, and producing hardware that simulates one way and synthesises another. Choosing <= for sequential logic is not a style preference; it is how you model the fact that every flip-flop samples its input at the same instant.
Before you start
- Boolean logic and basic gates
- Flip-flops, registers and the idea of a clock edge
- Binary and hexadecimal number representation
What you will be able to do
- Describe combinational and sequential logic that synthesises into the hardware you intended
- Choose blocking or non-blocking assignment correctly, and explain the consequence of each
- Build a module hierarchy and connect instances by name
- Write a parameterised module that scales by width or depth
- Code a finite state machine and reason about its reset and output timing
- Write a testbench that drives stimulus and checks results
The learning path
- Hardware, not softwareWhy every block is concurrent, and what a module really describes
- Nets and variableswire vs reg, and which one a construct is allowed to drive
- Continuous assignmentDataflow modelling for combinational logic
- Procedural blocksinitial and always, sensitivity, and what triggers evaluation
- Blocking vs non-blockingModelling combinational and sequential timing correctly
- Hierarchy and parametersInstantiating modules and scaling them by parameter
- Generate constructsReplicating structure at elaboration time
- State machinesEncoding state, next-state logic and registered outputs
- TestbenchesDriving stimulus and checking behaviour in simulation
Core concepts
New to Verilog? Work through the curriculum in order — each lesson assumes the one before it, and the sequence is what turns the roadmap above into working knowledge.
Already working with it? Use the core-concept links above to jump straight to the topic you need; each one opens the lesson that covers it in most depth.
Where this leads
Standards: IEEE 1364 / IEEE 1800 — The Verilog and SystemVerilog language standards this track is authored against