AMBA APB — Tutorials · VLSI Mentor

143Total chapters

20Modules

143Chapters live

20 / 20Active modules

Built on real register access

Two-phase transfers, wait states, and PREADY handshake taught as the way peripherals actually answer the CPU — not a flat signal list.

Interview-ready depth

A dedicated interview module plus per-chapter interview weighting — PENABLE traps, PREADY timing, wait-state corner cases, and waveform reading.

Design → verify → debug

RTL templates (APB slave, register bank, AHB-to-APB bridge), SVA/UVM verification, and waveform-based debugging — the full engineering loop.

AMBA APB Complete Curriculum

Your Learning Roadmap

143 chapters · 20 modules — two-phase transfers, PREADY handshake, and the AHB bridge.

143of 143 chapters live

100% complete

Module 1

APB Foundations

1.1Why APB Exists 1.2The AMBA Family Overview 1.3APB vs AHB vs AXI 1.4The Low-Speed Peripheral Philosophy 1.5The Register-Access Mental Model 1.6Typical APB SoC Architecture

Module 2

APB Architecture

2.1Manager and Subordinate Model 2.2APB Bus Topology 2.3APB Transfer Overview 2.4The Address Phase (Setup) Anatomy 2.5The Access Phase Anatomy 2.6The Transfer Lifecycle FSM 2.7APB Version Evolution

Module 3

APB Signals Deep Dive

3.1PCLK — The Bus Clock 3.2PRESETn — The Active-Low Reset 3.3PADDR — The Address Bus 3.4PSEL — The Subordinate Select 3.5PENABLE — The Access Strobe 3.6PWRITE — The Direction Bit 3.7PWDATA — The Write Data Bus 3.8PRDATA — The Read Data Bus 3.9PREADY — The Ready Handshake 3.10PSLVERR — The Subordinate Error 3.11PSTRB — The Write Strobes 3.12PPROT — The Protection Attributes

Module 4

APB Transfer Mechanics

4.1The IDLE State 4.2The Setup Phase in Depth 4.3The Access Phase in Depth 4.4Anatomy of a Read Transfer 4.5Anatomy of a Write Transfer 4.6Single-Cycle Transfers 4.7Multi-Cycle Transfers 4.8Transfer Completion Rules

Module 5

Setup and Access Phases — Deep Drill

5.1Why APB Uses Two Phases 5.2Setup-Phase Timing Anatomy 5.3Access-Phase Timing Anatomy 5.4PENABLE Behaviour Deep Dive 5.5Signal-Stability Requirements 5.6Legal and Illegal Transitions 5.7Two-Phase Timing Diagrams 5.8Setup / Access Interview Traps

Module 6

Read Transactions

6.1The APB Read Flow 6.2PRDATA Timing 6.3PREADY Interaction in Reads 6.4Read Wait States 6.5Read Error Responses 6.6Read Waveform Analysis

Module 7

Write Transactions

7.1The APB Write Flow 7.2PWDATA Timing 7.3Write Completion Contract 7.4Write Wait-State Behaviour 7.5Write Error Handling 7.6Write Waveform Analysis

Module 8

Wait States and PREADY

8.1Why Wait States Exist 8.2Slow-Peripheral Behaviour 8.3PREADY Timing 8.4Transfer-Extension Mechanics 8.5Multiple Wait Cycles 8.6PREADY Common Design Bugs 8.7Wait-State Verification Challenges

Module 9

Error Handling

9.1PSLVERR Behaviour 9.2Error-Response Timing 9.3Illegal-Address Access 9.4Protection Violations 9.5Peripheral Failure Modes 9.6Error Debug Methodology

Module 10

APB2 / APB3 / APB4 Evolution

10.1APB2 Baseline 10.2APB3 Introduction 10.3APB4 Introduction 10.4PREADY Introduction Rationale 10.5PSLVERR Introduction Rationale 10.6PSTRB Feature Deep Dive 10.7PPROT Feature Deep Dive

Module 11

APB Slave Design

11.1Register-Bank Design 11.2The Address Decoder 11.3Read-Data Mux 11.4Write Logic 11.5PREADY Generation 11.6PSLVERR Generation 11.7Slave Reset Behaviour 11.8Slave RTL Templates

Module 12

APB Register Maps

12.1CSR Design Fundamentals 12.2Address-Allocation Strategy 12.3Reserved Fields 12.4Read-Only Registers 12.5Write-Only Registers 12.6Status Registers 12.7Configuration Registers 12.8Register-Map Industry Best Practices

Module 13

APB Bridges

13.1AHB-to-APB Bridge 13.2AXI-to-APB Bridge 13.3Protocol-Conversion Mechanics 13.4Wait-State Propagation 13.5Error Propagation 13.6Bridge Address Mapping 13.7Bridge FSM Design

Module 14

APB Performance

14.1APB Latency Anatomy 14.2APB Throughput 14.3Why APB Is Not Pipelined 14.4Bus Utilisation 14.5Peripheral-Access Cost 14.6APB System Impact

Module 15

APB Verification

15.1APB Protocol-Rules Catalogue 15.2APB Assertions 15.3APB Monitors 15.4APB Scoreboards 15.5APB Functional Coverage 15.6The UVM APB Agent 15.7APB Negative Testing 15.8APB Corner Cases

Module 16

APB Debugging

16.1PENABLE Errors 16.2PSEL Bugs 16.3PREADY Stuck Low 16.4Incorrect PRDATA 16.5Write Corruption 16.6Address-Decode Bugs 16.7Bridge Bugs

Module 17

APB Interview Mastery

17.1Beginner Interview Questions 17.2Intermediate Interview Questions 17.3Advanced Interview Questions 17.4RTL Interview Questions 17.5Verification Interview Questions 17.6Waveform Interview Questions 17.7Debug Interview Questions

Module 18

Industry Case Studies

18.1UART APB Interface 18.2GPIO APB Interface 18.3Timer Peripheral 18.4Interrupt Controller 18.5Watchdog Timer 18.6SPI Controller 18.7I²C Controller

Module 19

APB Design-Review Checklist

19.1RTL Review Checklist 19.2Verification Review Checklist 19.3Integration Review Checklist 19.4Timing Review Checklist 19.5Debug Review Checklist

Module 20

APB Misconceptions Engineers Commonly Have

20.1“APB Is Always Single-Cycle”20.2“PENABLE Can Assert Immediately”20.3“PREADY Is Optional Everywhere”20.4“APB Needs Burst Support”20.5“APB Has No Timing Challenges”20.6“APB Can Be Pipelined”20.7“APB Has No Error Reporting”