AMBA APB · Module 3

PENABLE — The Access Strobe

PENABLE, the strobe that splits an APB transfer into its two phases — low in setup, high in access — and the PENABLE-low first cycle that gives a subordinate its decode window.

Module 2 taught you that PENABLE "marks the access phase." That is the right role, but to drive or sample PENABLE correctly in real RTL you need its exact contract: when it is low, when it is high, who drives it, and the rule that makes a trivially simple subordinate correct. PENABLE is the one bit that splits every APB transfer into its two phases — low for the setup cycle, high for the access cycle — and the precise shape of that one bit is the heart of the two-phase protocol. The single idea to carry: PENABLE is low for exactly the first cycle of every transfer, and that deliberate low cycle is what gives a subordinate a settled window to decode before it must act.

1. What problem is being solved?

The problem is telling the subordinate, unambiguously, which cycle is "get ready" and which cycle is "do it now."

A subordinate sees an address and control appear on the bus. On its own, that is not enough information to act safely: if it commits the instant the address shows up, it has no settled cycle to decode and prepare, and a slow combinational decode races the commit. APB solves this with one extra signal that times the access:

PENABLE low marks the setup cycle — the access is presented, and the subordinate uses this cycle to decode and prepare. Nothing commits.
PENABLE high marks the access cycle — the access is now being performed, and (with PREADY) completes here.

That single bit is the whole mechanism that turns "an address appeared" into a clean, two-step "present, then perform." Without it, APB would have no way to give the subordinate its decode window, and the protocol's defining simplicity would be gone.

2. Why the lifecycle view is not enough

Module 2 told you PENABLE is the access-phase marker — a lifecycle role. That is true, but a role is not a waveform. To wire PENABLE into a real manager or check it in a real subordinate, you need its exact electrical contract, and the lifecycle view leaves three things unstated:

The exact timing: low for exactly one cycle, then high. PENABLE is low for the single setup cycle of every transfer and goes high on the next cycle. It is never high in the first cycle, and it is never low for two setup cycles. The lifecycle says "setup then access"; the signal contract says one cycle low, then high until done.
Who drives it, and from what. PENABLE is driven by the manager (the bridge), derived directly from its transfer FSM — it is state == ACCESS, nothing more. A subordinate never drives PENABLE; it only samples it.
What it does during wait states. When the subordinate stretches the access by holding PREADY low, PENABLE stays high for the whole wait — it does not toggle. The phase marker holds; only completion waits.

Knowing the role tells you what PENABLE means; knowing the contract tells you what PENABLE looks like on the wire — which is what you actually need to build or debug a transfer.

3. The signal's mental model

The model: PENABLE is the "go" flag that follows the "get set" cycle.

Think of a sprinter's start. "On your marks, get set" is the setup cycle — the runner is in position but has not moved (PENABLE low, the access presented but not performed). "Go!" is the access cycle — PENABLE rises, and the run happens. The crucial detail is that "get set" always comes first and lasts exactly one beat: you never shout "Go!" before the runner is set, and you do not linger on "get set." That is the PENABLE-low-first-cycle rule made intuitive.

Three refinements make the model precise:

One "get set" beat, always. PENABLE is low for exactly the first cycle of every transfer — the subordinate's guaranteed decode window. APB never skips it and never doubles it.
"Go" holds until the race is finished. Once PENABLE goes high it stays high through the entire access phase, including any wait-state cycles, until PREADY high completes the transfer. The "go" flag does not blink while you wait for the finish.
PENABLE marks the phase, not the finish. "Go" means the access is being performed, not that it is done. Completion is the separate condition PENABLE and PREADY both high. Reading PENABLE high as "done" is the classic error.

4. Real SoC / hardware context

In hardware, PENABLE is the cleanest possible output of the manager's transfer FSM: it is high in exactly one state. The bridge that runs the lifecycle drives PENABLE straight from its state register — no extra logic, no decode.

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Snippet

// PENABLE generation in the APB manager (teaching sketch — not a full bridge).
// PENABLE is purely a function of the FSM state: high only in ACCESS.
typedef enum logic [1:0] { IDLE, SETUP, ACCESS } apb_state_t;
apb_state_t state;
 
// The whole contract in one line: low in IDLE/SETUP, high in ACCESS.
assign penable = (state == ACCESS);
 
// PSEL is high in SETUP and ACCESS; the SETUP cycle is therefore the unique
// cycle where PSEL is high and PENABLE is low — the subordinate's decode window.
assign psel = (state == SETUP) || (state == ACCESS);

Two facts fall straight out of that one assignment. First, because the FSM spends exactly one cycle in SETUP before moving to ACCESS, PENABLE is guaranteed low for exactly one cycle per transfer — the PENABLE = 0 first-cycle rule is structural, not something the designer must police. Second, because the FSM stays in ACCESS while PREADY is low, PENABLE automatically holds high through wait states; the designer gets the correct hold behaviour for free.

On the subordinate side, PENABLE is the signal that gates committing actions. A correct subordinate decodes in the setup cycle (PSEL high, PENABLE low) and commits in the access cycle — but only at completion. The canonical commit condition is PSEL and PENABLE and PREADY all high, never PENABLE alone, because PENABLE is high for every wait cycle too. The subordinate uses PENABLE to know it is in the access phase, and PREADY to know the access is finishing.

Figure 1 — PENABLE across a transfer with one wait state, against PCLK. In the first cycle (SETUP) PSEL is high and PENABLE is low — this is the unique PSEL-high, PENABLE-low cycle, the subordinate's decode window. PENABLE then goes high and stays high for the rest of the transfer: across the wait-state cycle (PREADY low, the access held) and the completion cycle (PREADY high). The diagram shows PENABLE marking the whole access phase, holding high through the wait, and that completion is where PENABLE and PREADY are both high — not where PENABLE first rises.

5. Engineering tradeoff table

PENABLE is a deliberately minimal signal. Each property trades a capability APB does not need for the simplicity it does.

`PENABLE` property	What it gives up	What it buys	Why it is correct for APB
Low for exactly one setup cycle	A possible one-cycle transfer	A guaranteed decode window before commit	A free cycle for sparse, latency-insensitive traffic
Driven purely from FSM state	Independent enable control	Trivial, glitch-free generation (`state == ACCESS`)	One assignment is cheaper and safer than custom logic
Held high through wait states	A per-cycle "still going" signal	Backpressure handled by `PREADY` alone	One signal owns timing; `PENABLE` just marks the phase
Manager-driven only	Subordinate influence on the phase	One driver, no contention	The subordinate's only lever is `PREADY`
Marks the phase, not completion	A single "done" strobe	A clean split of "performing" vs "finished"	Completion needs `PREADY` too; separating them is robust

The throughline: PENABLE does exactly one job — mark the access phase — and does it as a one-line function of state. Everything about timing-with-the-subordinate is delegated to PREADY, which keeps PENABLE itself dead simple and impossible to get subtly wrong.

6. Common RTL / waveform mistakes

Misconceptions to unlearn

"PENABLE is high in the first cycle of a transfer." No. PENABLE is low for the first (setup) cycle of every transfer and high from the second cycle. A waveform showing PENABLE high in the first cycle is broken.
"PENABLE high means the transfer is complete." No. PENABLE high means you are in the access phase — it is high on wait cycles too. Completion is PENABLE and PREADY both high.
"PENABLE toggles low during a wait state." No. While PREADY is low, PENABLE stays high; the access is held, not restarted. PENABLE only returns low for the next transfer's setup cycle.
"The subordinate should commit a write whenever PENABLE is high." No. Committing on PENABLE alone captures data during wait cycles, before the subordinate is ready. Gate commits on PSEL & PENABLE & PREADY.
"PENABLE and PSEL rise together at the start of a transfer." No. PSEL rises first (in setup) while PENABLE stays low; PENABLE rises one cycle later. That one-cycle gap is the decode window.
"PENABLE needs its own control logic." No. It is just state == ACCESS. Building custom enable logic is how you accidentally create glitches or break the one-cycle-low rule.

7. Interview framing

PENABLE is a favourite because a precise answer proves you understand the two-phase model at the signal level, and a vague one ("it enables the transfer") proves you do not. Interviewers ask "what does PENABLE do?" or "when is PENABLE low?"

The strong answer states the contract, not just the role: PENABLE is low for exactly the first (setup) cycle of every transfer and high from the access cycle onward, held high through any wait states until PREADY completes the transfer; it is driven by the manager as state == ACCESS. Then deliver the two depth points: the PENABLE-low first cycle is the subordinate's decode window (the reason APB is two-phase), and PENABLE marks the phase, not completion — a write commits only when PSEL, PENABLE, and PREADY are all high, never on PENABLE alone. That distinction between "in the access phase" and "the access finished" is exactly what separates an engineer who can debug an APB waveform from one who cannot.

8. Q&A

9. Practice

Draw the waveform. For a transfer with one wait state, draw PSEL, PENABLE, and PREADY across all cycles and label which cycle is setup, which are access, and which is completion.
State the rule. From memory, write the one-line RTL that generates PENABLE and explain why it guarantees the PENABLE-low first cycle.
Find the bug. A waveform shows PENABLE high in the same cycle PSEL first rises. State which rule is broken and what the subordinate loses as a result.
Gate the commit. Write the condition a subordinate should use to capture a write, and explain why gating on PENABLE alone is wrong when the access has a wait state.
Trace the hold. For a two-wait-state read, state the value of PENABLE on each cycle and confirm it never toggles until the next transfer.

10. Key takeaways

PENABLE splits every APB transfer into two phases: low for the setup cycle, high for the access cycle(s). That one bit is the two-phase protocol.
PENABLE is low for exactly the first cycle of every transfer — the subordinate's guaranteed decode-and-prepare window, and the reason APB is two-phase rather than one-cycle.
It is manager-driven, straight from the FSM: assign penable = (state == ACCESS). No custom logic, one driver, glitch-free.
It holds high through wait states. While PREADY is low the access is held and PENABLE does not toggle; backpressure is owned by PREADY, not PENABLE.
PENABLE marks the phase, not the finish. A write commits, and read data is valid, only when PSEL, PENABLE, and PREADY are all high — never on PENABLE alone.
The classic errors are timing errors: PENABLE high in the first cycle, PENABLE read as "done," or PENABLE toggling during a wait. Each breaks the decode window or the phase/completion split.