PWRITE — The Direction Bit

Module 2 named the two kinds of access — a write that pushes data out and a read that pulls data back — and treated direction as part of the lifecycle. That was the right role, but to wire PWRITE into real RTL you need its exact contract: what it selects, who drives it, and when it must hold. PWRITE is the single bit that sets a transfer's direction — 1 for a write, 0 for a read — and that one bit is all APB needs because a transfer is exactly one direction. The single idea to carry: PWRITE does not move any data itself; it selects which data bus is meaningful — PWDATA outbound for a write, PRDATA inbound for a read — and it is presented in SETUP and held stable through ACCESS like every other access-defining signal.

1. What problem is being solved?

The problem is telling the subordinate which way the data flows for this transfer — without which neither side knows whether to push or pull.

A subordinate that is selected and given an address still does not know what to do with the access. Should it capture incoming data into a register, or should it drive a register's value back onto the bus? Those are opposite hardware actions on opposite buses, and only one of them is correct. APB answers with one bit:

• PWRITE high (1) means write — the manager is pushing data to the subordinate, which the subordinate captures into the addressed register.
• PWRITE low (0) means read — the subordinate is pushing data back to the manager, driving the addressed register's value onto the read bus.

That single bit is the whole mechanism that decides direction. Without it, the address would say where but never which way, and the subordinate could not tell a register write from a register read.

2. Why the lifecycle view is not enough

Module 2 told you that a transfer is "a write or a read" — a lifecycle distinction. That is true, but a named kind of access is not a signal contract. To drive PWRITE in a real manager or decode it in a real subordinate, you need its exact electrical behaviour, and the lifecycle view leaves three things unstated:

• Exactly what PWRITE selects. It does not carry data; it selects the active data bus. When PWRITE is 1, PWDATA is the meaningful bus and the manager drives it; when PWRITE is 0, PRDATA is the meaningful bus and the subordinate drives it. The other bus is don't-care for that transfer.
• Who drives it, and when it is valid. PWRITE is driven by the manager, presented in the SETUP cycle alongside PADDR, and held stable through ACCESS until completion. A subordinate never drives PWRITE; it only samples it.
• How the subordinate uses it. The subordinate uses PWRITE (together with the completion condition) to gate its write-enable on a write, or to drive its read multiplexer on a read. One bit steers two opposite pieces of logic.

Knowing the kind of access tells you what PWRITE means; knowing the contract tells you what PWRITE does on the wire — which is what you need to build or debug a transfer.

3. The signal's mental model

The model: PWRITE is a one-way street sign at the start of the transfer.

Picture a single road between the manager and the subordinate. Data can travel in only one direction at a time, and PWRITE is the sign that says which way for this trip. Set it to "write" and the road carries data outbound on PWDATA toward the subordinate; set it to "read" and the road carries data inbound on PRDATA back to the manager. You set the sign before the traffic moves — in SETUP — and you do not flip it mid-trip. Because every trip is one direction, one sign is all you ever need.

Three refinements make the model precise:

• PWRITE selects, it does not carry. The bit itself moves no payload. It chooses which of the two data buses is the live one for this transfer; the data rides on PWDATA or PRDATA, never on PWRITE.
• The sign is set in SETUP and held. PWRITE is presented in the setup cycle with the address and held stable through the whole access phase, including any wait states, until PREADY completes the transfer. Changing direction after the access is presented is a protocol violation.
• One bit suffices because a transfer is one direction. APB never mixes a read and a write in the same transfer, so direction is a single Boolean, not a field. That is why APB needs exactly one direction bit and no more.

4. Real SoC / hardware context

In hardware, PWRITE is the cleanest possible steering bit. The manager — the AHB/AXI-to-APB bridge — drives PWRITE straight from the request it is forwarding: a firmware store becomes PWRITE high, a firmware load becomes PWRITE low. There is no decode, no computation; the direction of the upstream access is PWRITE.

On the subordinate side, PWRITE is the select line for two opposite actions. For a write (PWRITE high), the subordinate qualifies its register write-enable with PWRITE and the completion condition, so the addressed register captures PWDATA only at the completion cycle — never on direction alone. For a read (PWRITE low), the subordinate uses PWRITE to enable its read path: it selects the addressed register through the read multiplexer and drives that value onto PRDATA for the manager to sample at completion. The same one bit gates a capture on one side of the transfer and a drive on the other.

The completion qualifier matters because PWRITE alone is not a commit signal — it is true for the whole transfer, including the setup cycle and any wait cycles. A subordinate that wrote its register the moment PWRITE is high would capture data before the access is performed. Direction tells the subordinate which way; completion tells it now.

5. Engineering tradeoff table

PWRITE is a deliberately minimal signal. Each property trades a capability APB does not need for the simplicity it does.

The throughline: PWRITE does exactly one job — set direction — and stays orthogonal to what the data is and when it commits. That keeps the bit trivial to drive and impossible to misread, as long as you remember it selects rather than carries and commits only with completion.

6. Common RTL / waveform mistakes

7. Interview framing

PWRITE looks too simple to ask about, which is exactly why a vague answer ("it picks read or write") fails to impress and a precise one stands out. Interviewers ask "what does PWRITE do?" or "how does the subordinate know whether to capture or drive data?"

The strong answer states the contract, not just the role: PWRITE is a single manager-driven direction bit — 1 for write, 0 for read — presented in SETUP and held stable through ACCESS until completion; it selects which data bus is meaningful (PWDATA outbound for a write, PRDATA inbound for a read) rather than carrying any data itself. Then deliver the two depth points: PWRITE selects, it does not carry — the payload always lives on the data buses — and the subordinate uses PWRITE with the completion condition to gate its write-enable or to drive its read mux, so a write commits only at PSEL & PENABLE & PREADY, never on PWRITE alone. Closing with "one bit is all APB needs because a transfer is exactly one direction" shows you understand why the contract is shaped this way.

8. Q&A

9. Practice

1. State the contract. From memory, write the two meanings of PWRITE, who drives it, when it is presented, and how long it must hold stable.
2. Name the bus. For PWRITE high and for PWRITE low, state which data bus is meaningful, which side drives it, and which bus is don't-care.
3. Gate the write. Write the condition a subordinate should use to capture write data, and explain why gating on PWRITE alone is wrong.
4. Find the bug. A waveform shows PWRITE changing value between the SETUP and ACCESS cycles of one transfer. State which rule is broken and what the subordinate could do wrong as a result.
5. Justify the single bit. In two sentences, explain why APB needs only one direction bit and does not require separate read-enable and write-enable signals.

10. Key takeaways

• PWRITE is the single direction bit: 1 means write, 0 means read. One bit is all APB needs because a transfer is exactly one direction.
• PWRITE selects, it does not carry. It chooses which data bus is meaningful — PWDATA outbound for a write, PRDATA inbound for a read — while the payload always rides on those data buses.
• It is manager-driven, straight from the upstream access. A store becomes PWRITE high, a load becomes PWRITE low; the subordinate only samples PWRITE.
• It is presented in SETUP and held stable through ACCESS until completion, exactly like PADDR. Changing direction mid-transfer is a protocol violation.
• The subordinate uses PWRITE with completion to gate its write-enable or drive its read mux — a write commits only at PSEL & PENABLE & PREADY, never on PWRITE alone.
• Only the selected bus is valid. On a write PRDATA is don't-care; on a read PWDATA is don't-care — direction tells you which one to trust.