APB vs AHB vs AXI

You know that APB, AHB, and AXI carry different traffic. This chapter shows how they differ in structure — and makes one idea unmistakable: the three buses are separated by concurrency, not by clock speed. APB does one self-contained transfer at a time; AHB pipelines so the next transfer's setup overlaps the current one; AXI runs many independent transactions in parallel and lets them complete out of order. Holding that single axis — none, then serial-with-overlap, then parallel — is worth more than any signal list, and it is exactly what makes APB the cheap, simple, low-bandwidth member it is. This is a conceptual chapter; the cycle-level timing of an APB access is reserved for the register-access model.

1. What problem is being solved?

The problem is comparing the three buses at the level that actually matters — their transfer structure — rather than the level that misleads, their clock speed.

The single most useful comparison is along the concurrency axis:

• APB performs a single two-phase transfer — a setup step then an access step — and finishes it before starting the next. No overlap, no parallelism.
• AHB is pipelined: while one transfer's data is moving, the next transfer's address is already being presented. Accesses run back to back on a shared bus, but still one access path at a time.
• AXI splits a transaction across decoupled channels with many outstanding transactions, completing out of order. Genuine concurrency.

Everything else — bandwidth, complexity, cost — follows from where each sits on that axis. Comparing by "slow, medium, fast" hides the mechanism; comparing by concurrency explains it.

2. Why existing buses were not the right fit

Each transfer style exists to serve a different traffic density, and the styles are not interchangeable — which is why you cannot make APB into AHB by tuning it.

APB has no overlap because its traffic is sparse: the dead time between rare register pokes is free, so there is nothing to gain from pipelining and real cost to add it. AHB removes the dead time with overlap because its denser backbone traffic cannot afford it. AXI removes the serialization itself with parallel, outstanding, reorderable transactions because its traffic has many independent streams and deep latency to hide.

This is why "just clock APB faster" is the wrong instinct for throughput. Raising the bus clock shortens each transfer, but APB still does one self-contained transfer at a time — it has no mechanism to overlap or parallelize. The limit is structural, not speed. A "faster APB" is still one transfer at a time; it never becomes AHB. To move past the limit you must change the transfer structure, which is exactly what AHB and AXI are. The earlier buses were not the right fit for denser traffic because their structure, not their clock, capped them — and the family answered each cap with a new structure, leaving APB to keep doing the one job its self-contained transfer is perfect for.

3. APB mental model

Feel the difference as a rhythm, one transfer per bus:

• APB is "announce, act, finish — then repeat." Every transfer is a complete little ceremony: present the access (SETUP), do it (ACCESS), done. The next transfer starts from scratch, with dead time between — and APB does not care.
• AHB is "act while announcing the next." As the current transfer's data moves, the next transfer's address is already presented. The same one road, but never idle between accesses — that overlap is pipelining.
• AXI is "fire many, collect later, in any order." Independent requests go out on separate channels; responses return whenever slaves are ready, possibly out of order, many in flight at once. Not one road kept busy — many conversations at once.

APB's own rhythm has just two beats. In SETUP, the manager selects the target (asserts its PSEL) and presents the address, direction, and write data, with the access strobe PENABLE held low — giving the subordinate a full cycle to decode. In ACCESS, PENABLE goes high, the access happens, and the subordinate signals completion with PREADY; a slow subordinate can hold PREADY low to stretch the access. Two beats, self-contained, then repeat — the simplest possible point on the concurrency axis.

4. Real SoC placement & hardware context

The three transfer styles map directly onto three very different amounts of logic — and that is where the cost difference lives, and why the styles dictate where each bus sits.

An APB subordinate needs almost nothing: an address decode to know it is selected (PSEL), a register write gated on the ACCESS phase, a read multiplexer, and a PREADY (a fast peripheral can tie it high). No pipeline, no outstanding-transaction tracking, no reordering — a correct one is a few dozen lines of RTL, verifiable almost exhaustively. An AHB subordinate must cope with pipelining: it sees the next transfer's address while finishing the current one, so it must capture address-phase information and use it a cycle later — meaningfully more complex. An AXI subordinate must handle five independent channels, multiple outstanding transactions, ordering rules, and response generation — a different order of complexity again.

This is the concrete payoff of APB's simplicity: the cheapest transfer style produces the cheapest, most verifiable interface, which is exactly why a large fan-out of simple peripherals gets APB ports, not AHB or AXI ports. It is also why the bridge between a fast bus and APB is non-trivial: the fast side expects a pipelined or decoupled response, but APB can only do its self-contained two-phase ceremony, one at a time. The bridge accepts the fast-side transaction, runs the APB SETUP/ACCESS sequence, waits on PREADY, and only then completes upstream. A burst on the fast side becomes a sequence of separate APB transfers, each paying APB's full two-phase cost — fine for control traffic, and exactly why you never route data traffic through the bridge.

5. Engineering tradeoffs

The comparison is the tradeoff. The table makes each bus's structural choice explicit; read it as the same question answered three ways.

The throughline: capability is not free. APB's lack of pipelining and concurrency is not a deficiency relative to AHB and AXI; it is the correct trade for traffic that would never use those features. You pick the leftmost sufficient point on the axis — APB for the control plane, AHB for a few moderate masters, AXI for many concurrent high-bandwidth ones.

6. Common RTL / architecture mistakes

7. Interview framing

This comparison is a favorite opener because a clean answer instantly separates people who memorized signal lists from people who understand bus architecture.

The strong answer names the concurrency axis explicitly and anchors APB on its two-phase transfer: APB does one self-contained two-phase transfer — SETUP then ACCESS — at a time, with no pipelining and no concurrency; AHB pipelines so the next transfer's address overlaps the current data on a shared bus; AXI decouples into independent channels with many outstanding, reorderable transactions. Then close with the trap: the buses differ by concurrency, not clock speed, so a faster APB never becomes AHB. What interviewers are really probing is whether you reason about transfer structure — mentioning two-phase SETUP/ACCESS for APB, pipelining for AHB, decoupled channels for AXI — because that shows you could actually implement or debug one of these interfaces.

8. Q&A

9. Practice

1. Place the axis. Put APB, AHB, and AXI on the concurrency axis and give the one-word descriptor for each (none / overlap / parallel).
2. Name the rhythm. From memory, describe an APB write in two phases: what each of PSEL, PENABLE, PADDR, PWDATA, and PREADY does in SETUP and in ACCESS.
3. Spot the trap. A colleague says "we'll get more peripheral throughput by doubling the APB clock." Explain why that is structurally limited and what would actually be needed.
4. Match traffic to style. For configuring a timer, streaming a video frame, and a CPU fetching a cache line — name the transfer style (and bus) that fits, and why.

10. Key takeaways

• The three buses differ by concurrency, not clock speed: APB has none, AHB serializes on a shared bus but pipelines hand-offs, AXI runs many transactions in parallel and reorders them.
• APB's whole protocol is one two-phase transfer: SETUP (PSEL high, PENABLE low — decode/prepare) then ACCESS (PENABLE high — do it and sample PREADY), self-contained and unpipelined.
• PENABLE is the defining signal — low marks SETUP, high marks ACCESS; the 'announce then act' split makes a trivially simple subordinate correct.
• PREADY is APB's only flex — a slow subordinate holds it low to stretch ACCESS. (Added in APB3; APB2 used fixed two-cycle accesses.)
• Transfer style dictates cost — APB's self-contained transfer yields the cheapest, most verifiable interface, which is why slow peripherals get APB ports.
• A faster APB never becomes AHB. The limit is structural; more throughput requires changing buses.