AMBA APB · Module 5

Setup-Phase Timing Anatomy

The setup phase cycle by cycle — the launch edge where PSEL rises with PENABLE low and the access-defining signals become valid together, the one-cycle decode window, and the unconditional move into access.

The setup-phase mechanics chapter named the setup phase and gave you its signature — PSEL high while PENABLE is low. This deep-drill chapter answers a sharper question: on which edge does setup begin, what becomes true on that exact edge, and what does the subordinate do with the cycle it is given? The single idea to carry: setup is one cycle long, it is entered on the launch edge where PSEL rises and every access-defining signal becomes valid together, and that cycle exists to hand the subordinate a guaranteed decode-and-prepare window — after which the move into access is unconditional. Everything here is that sentence read edge by edge against PCLK.

1. What problem is being solved?

The problem is timing the moment of presentation precisely — when the access becomes visible, and how long the subordinate has before anything is performed.

A subordinate cannot decode an address, choose a register, and ready its read mux or write enable in zero time. It needs a settled cycle where the access is fully on the bus and provably will not move. APB's answer is to make presentation a timed event: on one rising PCLK edge — the launch edge — the manager raises the targeted PSEL, keeps PENABLE low, and drives every access-defining signal valid simultaneously. From that edge, three timing facts hold at once:

The launch edge is a single, identifiable instant. PSEL transitions low→high on it; before it the bus was idle, after it a transfer is in flight. There is exactly one such edge per transfer.
Everything the access is made of becomes valid together on that edge. PADDR, PWRITE, PWDATA, PSTRB, and PPROT all turn valid on the same edge — not staggered. The subordinate sees a complete, settled access, not a partially formed one.
PENABLE low timestamps this as the decode cycle. While PENABLE is low, the access is presented but unperformed — the subordinate is free to decode without anything committing under it.

So the problem solved is temporal: APB guarantees one clean cycle, delimited by precise edges, in which the access exists and nothing yet acts on it.

Figure 1 — the single setup cycle at timing resolution against PCLK. On the launch edge, PSEL rises from low to high while PENABLE is held low, and PADDR, PWRITE, PWDATA, PSTRB, and PPROT all become valid together on that same edge and are stable from it. PENABLE held low is what marks this cycle as setup. Setup lasts exactly one cycle; on the next edge PENABLE rises and the bus moves unconditionally into access. The figure stresses the two edges — the launch edge that opens setup and the setup-to-access boundary — and that the access-defining signals are valid from the first.

2. Why the previous model is not enough

Module 4 — the setup-phase mechanics gave you what the setup phase is: its PSEL-high, PENABLE-low signature, the access it presents, and the rule that the presented values are stable. That is the mechanics. This chapter drills the timing of that same cycle — the precise edges, what is valid on each, and the structure of the decode window — because the mechanics view leaves the temporal questions open, and timing bugs live exactly there.

Reasoning at the mechanics level leaves three things imprecise:

The launch edge is treated as "the start," not as a specific edge with simultaneity guarantees. Mechanics says the access is "presented in setup." Timing says: every access-defining signal turns valid on the same rising edge PSEL does — not one a little later. That simultaneity is what lets the subordinate decode a complete access in one cycle; a staggered presentation would break it even though the lifecycle still looks like setup.
"One cycle" is a duration; the edges that bound it are what you read on a trace. Setup opens on the launch edge and closes on the setup-to-access edge where PENABLE rises. Knowing it is "one cycle" does not tell you those are two distinct, named edges — and that the closing edge is unconditional, unlike the completion edge which waits on PREADY.
The decode window is named but not structured. Mechanics says the subordinate "decodes in setup." Timing asks: decodes what, into what, gated by what? The held address feeds a combinational decode that prepares a register select and a write enable — and the commit gate, held by PENABLE low, stops any of it from landing. That structure is what the setup cycle actually buys.

So the model to add is the edge-level reading: the launch edge with its simultaneity, the two edges that bound the cycle, and the internal structure of the decode-and-prepare window. (For how long the presented values must then stay frozen, this chapter forward-references the signal-stability requirements; here the focus is the setup cycle's own anatomy.)

3. Mental model

The model: setup is the starting gun and the one-second head start, fired on a single edge. The launch edge is the gun — everything that defines the race (the lanes, the runners, the distance: PADDR, PWRITE, PWDATA, PSTRB, PPROT) is set on that instant. The one cycle that follows is the head start: the subordinate gets exactly one settled beat to read the lanes and set its feet, and on the next edge the race is on, no matter what.

Three refinements make the timing precise:

One edge sets everything. The access-defining signals do not trickle in — they are all valid on the launch edge, together. A subordinate that latches or decodes off that edge sees a coherent, complete access in a single cycle.
The cycle is bounded by two edges, and only the closing one matters for sequencing. The launch edge opens setup; the next rising edge raises PENABLE and enters access. That closing edge fires unconditionally — there is no handshake on it. The handshake (PREADY) lives later, at completion.
The cycle is a window, not an action. Nothing is committed in setup. The subordinate decodes and prepares; the commit gate stays shut. The value of the cycle is purely the time it grants — a guaranteed beat to be ready before the access is performed.

Figure 2 — what the subordinate does inside the setup cycle. The held, now-valid PADDR, PWRITE, and PSTRB feed combinational logic: an address decoder turns PADDR into a register select, a direction-and-strobe block turns PWRITE and PSTRB into a prepared write-enable, and a read-mux select picks the source register for a read. All of this reaches a commit gate held shut by PENABLE low — nothing is written and no PRDATA is driven. The setup cycle buys exactly this guaranteed decode-and-prepare window, so when PENABLE rises into access the subordinate can act immediately at completion.

4. Real SoC / hardware context

In silicon the launch edge is the edge the manager's transfer FSM takes leaving IDLE: it asserts the targeted PSEL, drives the registered access-defining signals onto the bus, and holds PENABLE low. Because those signals are registered, they all change on the same clock edge by construction — the simultaneity guarantee is not extra logic, it falls out of presenting from a single register stage. One cycle later the FSM raises PENABLE, unconditionally, and the bus is in access.

The subordinate side is where the setup cycle earns its keep. The held PADDR drives a combinational address decoder that produces a register select; PWRITE and PSTRB produce a prepared write-enable; the same decode picks the read-mux source. All of this settles during the setup cycle, but it is gated — the actual register write and the PRDATA drive are qualified by the access/completion condition, so nothing lands. The setup cycle is precisely the slack that lets this combinational decode resolve before it is needed.

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Snippet

// Subordinate combinational decode off the HELD setup-phase signals:
// register select and a PREPARED write-enable are computed, but committing
// is gated downstream by the access/completion condition (not shown here).
logic        sel_reg0, sel_reg1;
logic        wen_prepared;
 
always_comb begin
  sel_reg0     = (paddr[7:4] == 4'h0);   // address decode → which register
  sel_reg1     = (paddr[7:4] == 4'h1);
  wen_prepared = pwrite && (|pstrb);     // direction + strobe → prepared, not committed
end
// NOTE: sel_* and wen_prepared are READY by the end of SETUP. They only take
// effect when the access commits at completion — the setup cycle is the slack
// that lets this decode settle before PENABLE rises into ACCESS.

That is the load-bearing point of the timing view: the manager spends one fixed cycle and the unconditional exit so the subordinate's decode has a guaranteed window to resolve. The presented values must then stay byte-for-byte stable from this launch edge until completion — the contract drilled in the signal-stability requirements — because this decode's result is only consumed cycles later when the access commits.

5. Engineering tradeoff table

The timing shape of the setup cycle is a set of deliberate edge-level choices. Each spends a little to give the subordinate a precisely-timed, safe window.

Setup timing choice	What it gives up	What it buys	Why it is correct for APB
All access signals valid on the launch edge	Freedom to drive address/data late	A complete access visible in one settled cycle	A single register stage presents them together anyway
`PENABLE` low timestamps the decode cycle	A separate "decoding" strobe	One bit that bounds the window before commit	The same marker sequences both sides
Setup fixed at exactly one cycle	A tunable decode latency	A guaranteed, predictable decode window	One cycle is enough for a combinational decode
Unconditional setup-to-access edge	A way to stall in setup	A single place a transfer can wait (completion)	Only access needs elasticity; the entry stays fixed
Decode prepared, commit gated	Acting early on a fast decode	A decode that cannot corrupt state before commit	Commit must align with the completion handshake

The throughline: APB times the setup cycle as one fixed beat bounded by a launch edge and an unconditional exit, spending that beat purely to give the subordinate slack to decode. All the waiting is pushed to completion, keeping the entry edge trivial to drive and to verify.

6. Common RTL / waveform mistakes

Misconceptions to unlearn

"PSEL and PENABLE rise on the same edge to start a transfer." No. On the launch edge PSEL rises while PENABLE stays low; PENABLE rises one edge later. Rising them together skips the setup cycle entirely — there is no decode window, and the trace is illegal.
"The access-defining signals can settle a cycle after PSEL rises, as long as they are valid before access." No. They must be valid on the launch edge, together with PSEL. A staggered presentation shortens or destroys the decode window even though the phase bands still read setup.
"Setup can take more than one cycle if the subordinate needs more decode time." No. Setup is fixed at exactly one cycle and its exit is unconditional. A subordinate that needs more time inserts wait states in access via PREADY; it cannot stretch setup.
"The setup-to-access edge waits on a handshake like completion does." No. The setup-to-access edge is unconditional — nothing gates it. Only the access-to-completion edge waits, on PREADY. Confusing the two is the classic setup-timing error.
"Something is written or read during the setup cycle since the decode is done." No. The decode and the prepared write-enable settle in setup, but the commit gate is held shut by PENABLE low. Nothing lands until the access commits at completion.
"The launch edge only needs PADDR valid; data can come in the access phase." No. For a write, PWDATA (and PSTRB) are valid on the launch edge alongside PADDR — the whole access is presented together, and held stable from that edge.

7. Interview framing

A senior APB question that separates rote answers from real understanding is "walk me through the setup cycle edge by edge — which edge starts it, what is valid when, and what gates the exit?" It probes whether you read APB at edge resolution, not just phase resolution.

Answer in three moves. First, the launch edge: on one rising PCLK edge PSEL goes low→high while PENABLE stays low, and on that same edge every access-defining signal — PADDR, PWRITE, PWDATA, PSTRB, PPROT — becomes valid together. Second, the window: that single cycle is the subordinate's guaranteed decode-and-prepare window — it resolves its address decode and prepares its write-enable or read mux, but the commit gate is held shut by PENABLE low, so nothing lands. Third, the exit: one edge later PENABLE rises into access, unconditionally — unlike the completion edge, which waits on PREADY. The depth signal that lands: name that the access-defining signals are valid on the same edge PSEL rises, and that the values then stay frozen from that edge until completion. An interviewer hears edge-level reasoning and knows you have actually timing-analysed an APB trace.

8. Q&A

9. Practice

Mark the two edges. On a trace of a transfer with one wait state, mark the launch edge and the setup-to-access edge, and state the PSEL/PENABLE transition on each.
Check simultaneity. Given a trace where PADDR is valid on the launch edge but PSTRB settles one cycle later, state whether it is legal and what the subordinate's setup-cycle decode is working from.
Time the window. For a transfer with two wait states, say how many cycles the setup phase lasts and on which edge the decode result is finally consumed.
Spot the skipped setup. A trace shows PSEL and PENABLE both rising on the same edge. Name what is missing and why the subordinate's decode is now unsafe.
Trace the commit gate. Explain why the subordinate's prepared write-enable settles in setup but the register is not written until completion, and which signal holds the commit gate shut during setup.

10. Key takeaways

Setup begins on the launch edge — the rising PCLK edge where PSEL goes low→high while PENABLE stays low; this is the single identifiable instant a transfer opens.
Every access-defining signal becomes valid together on that edge — PADDR, PWRITE, PWDATA, PSTRB, PPROT — not staggered, so the subordinate sees a complete access to decode in one cycle.
PENABLE low timestamps the cycle as decode-only — the access is presented but the commit gate is held shut, so nothing is written and no PRDATA is driven during setup.
Setup is exactly one cycle, bounded by two edges — the launch edge that opens it and the unconditional setup-to-access edge where PENABLE rises; only the later completion edge waits on PREADY.
The cycle exists to buy a guaranteed decode-and-prepare window — the held address resolves a register select and a prepared write-enable, ready before the access commits at completion.
The values are valid from the launch edge and stay frozen until completion — the simultaneity here and the stability contract there are what keep the subordinate's one-cycle decode valid for the whole transfer.