The beginner tier proves you know the signals; this tier proves you know the contract under stress — what happens when a transfer is extended, when it fails, and when transfers come back-to-back. Where the foundation questions ask "what is PSEL" and "name the two phases," the intermediate bank hands you the cases that bite real silicon: a subordinate that holds PREADY low for an unbounded number of cycles, an access that completes with PSLVERR asserted, signals that must stay frozen across both phases, and a byte-masked write that touches only some lanes. The single idea to carry: every intermediate question is a stress test of one of two anchors — the two-phase stability contract (PADDR/PWRITE stable, PENABLE only in ACCESS) or the completion handshake (PSEL & PENABLE & PREADY, with PSLVERR and PRDATA valid only on that edge). Name the anchor and the answer follows.

1. What this tier covers

This tier covers the mid-level mechanics that turn the static two-phase picture into a working bus: wait states and the PREADY handshake that produces them, the PSLVERR error path, the stability rules the protocol enforces across both phases, back-to-back transfers and the SETUP gap between them, the PSTRB byte strobes, PPROT protection attributes, and the throughput cost that wait states impose. These are the topics an interviewer reaches for once you have proven you know the signal list — they probe whether you understand how the bus behaves when a transfer is slow, when it errors, and when it is one of many in a stream.

The coverage map below groups the clusters and shows how they hang off the same two anchors that run through the whole protocol.

2. Why the foundation tier isn't enough

The beginner tier establishes a static picture: there are two phases, five-plus signals, and a completion handshake. That picture is correct, but it describes a single, fast, successful transfer. The intermediate tier removes all three of those comforts at once — the transfer can be slow (wait states), it can fail (PSLVERR), and it is rarely alone (back-to-back streams). Each removal exposes a question the static picture cannot answer.

• The static picture assumes PREADY is high immediately. Once you allow wait states, you have to answer: how long can PREADY stay low, who decides, what protects the manager from an infinite wait, and how is PREADY itself generated — combinational or registered? None of those are visible in a zero-wait waveform.
• The static picture assumes every transfer succeeds. PSLVERR introduces a failure axis: when a subordinate may assert it, how the manager must interpret it, and the strict rule that it is only meaningful on the completion edge. A candidate who has only seen successful transfers has never reasoned about the error path.
• The static picture shows one transfer in isolation. Real traffic is back-to-back, and the question becomes whether APB pipelines (it does not) and where the mandatory SETUP cycle sits between adjacent accesses — which directly drives throughput and bus utilisation.

So the model to add is not new signals — it is behaviour under stress: extension, failure, and streaming. Every question in this chapter lives in one of those three stresses, and every answer resolves back to the two anchors.

3. Mental model

The model: hold the two-phase contract and the completion handshake in your head, then ask what each stress does to them. Wait states stretch the ACCESS phase without touching SETUP; PSLVERR rides the completion edge and is invalid everywhere else; back-to-back removes the idle gap but never the SETUP cycle; strobes and attributes are just more signals bound by the same stability rule.

Three through-line concepts tie the whole tier together:

• The subordinate owns the length of a transfer; the manager owns its start. The manager drives address, control, and PENABLE; the subordinate decides when to complete by releasing PREADY. A wait state is simply the subordinate exercising that ownership — every cycle it holds PREADY low is one extra ACCESS cycle. This is why timeouts live at the manager: it cannot force completion, only give up.
• Everything that terminates a transfer is sampled on exactly one edge — the completion edge. PREADY, PRDATA (on a read), and PSLVERR are all evaluated together on the first cycle where PSEL & PENABLE & PREADY are high. Off that edge they carry no contractual meaning: PSLVERR high while PREADY is low is not an error, and PRDATA before completion is not data.
• Stability is the wall around the whole access, and it covers more signals than people remember. PADDR, PWRITE, PWDATA, and PSTRB and PPROT must all be stable from the start of SETUP through completion. PENABLE is the one control signal that intentionally changes — low in SETUP, high in ACCESS — because it is the phase marker.

A useful refinement: the throughput cost of waits is mechanical, not mysterious. A zero-wait transfer is 2 cycles; each wait state adds exactly 1; and because the next transfer must spend a SETUP cycle before its own ACCESS, a stream of zero-wait transfers runs at one completion every 2 cycles — a hard 50% ceiling on a non-pipelined bus.

4. Real SoC / hardware context

These topics are not abstractions — each maps to a concrete block on a real SoC's peripheral subsystem. Wait states appear the moment an APB subordinate fronts something slower than the bus clock: a flash controller that needs several cycles to return data, a register block behind a clock-domain crossing, or an analog/PHY register file that synchronises before responding. The subordinate holds PREADY low for exactly as many cycles as it needs, and the manager — typically an APB bridge translating from AXI or AHB — stalls in step. A well-designed bridge carries a timeout/watchdog so that a stuck subordinate (PREADY never rising) raises a bus error to software instead of hanging the whole interconnect; this is the manager's only defence because it cannot force a subordinate to complete.

PSLVERR is how those same blocks report trouble: an access to an unmapped offset within a peripheral's window, a write to a read-only register, a privilege violation flagged via PPROT, or a parity/ECC failure in the backing store. The subordinate asserts PSLVERR with PREADY on the completion edge, and the bridge converts it into the upstream protocol's error encoding (an AXI SLVERR, for instance). PSTRB shows up wherever a 32-bit APB data bus fronts byte- and halfword-addressable registers — a write of a single status byte must assert only the corresponding strobe so the other three lanes are untouched. And PPROT carries the security and privilege intent down from a system MPU/MMU so a peripheral can reject a non-secure or unprivileged access at the bus boundary. Every one of these is a line or two of RTL, and every interview question in this chapter is asking whether you understand the contract that line of RTL must honour.

5. Weak vs strong answer

This is the spine of the chapter: each row is a question the interviewer actually asks, the weak answer that gets a polite nod and a follow-up that exposes it, and the strong answer that closes the topic.

The throughline: every weak answer is vague where the contract is precise. "A few cycles," "whenever there's an error," "yes it overlaps" — each drops a hard rule the protocol enforces. The strong answer always names the exact boundary: unbounded-but-timed, completion-edge-only, frozen-except-PENABLE, never-pipelined.

6. Common mistakes / red flags

7. Interview framing

The framing that lands at this tier is name the stress, then name the anchor it bends. When handed an intermediate question, classify it first: is this about extension (wait states / PREADY), failure (PSLVERR), streaming (back-to-back / throughput), or stability (the two-phase freeze, strobes, attributes)? Then state which of the two anchors it touches — the two-phase contract or the completion handshake — and the precise answer falls out.

For example: "How long can PREADY stay low?" is an extension question touching the completion handshake; the answer is "unbounded — the subordinate owns length, the manager owns the timeout." "Can PADDR change after PENABLE rises?" is a stability question touching the two-phase contract; the answer is "no — everything but PENABLE is frozen through completion." The single strongest move at this tier is to volunteer the unifying observation that everything which terminates a transfer — PREADY, PRDATA, PSLVERR — is sampled on one edge, the completion edge, and is meaningless off it. That one sentence resolves the wait-state, error, and read-data questions simultaneously and tells the interviewer you see the protocol as a contract, not a list of waveforms. If you can also walk a wait-state-plus-error waveform (Figure 2) and point to the exact edge where the error is sampled, you have shown you've debugged the bus, not just memorised it.

8. Q&A

9. Practice

1. Name the stress and the anchor. For each of these questions, say whether it is an extension, failure, streaming, or stability question, and which anchor it touches: "Can PWDATA change after PENABLE rises?", "How long can PREADY stay low?", "Is PSLVERR valid during a wait cycle?", "Do back-to-back transfers skip SETUP?", "Does PSTRB apply to reads?"
2. Walk the waveform. From Figure 2, narrate the read cycle by cycle — SETUP, the wait-state ACCESS cycle, the completing ACCESS cycle — and point to the single edge where PREADY, PRDATA, and PSLVERR are all evaluated. Then state the total cycle count and the throughput loss versus zero-wait.
3. Do the throughput math. Compute the completions-per-cycle for a back-to-back stream with 0, 1, and 2 wait states per transfer using 1 / (2 + w), and explain why the SETUP cycle makes 50% the hard ceiling for the zero-wait case.
4. Defend the freeze. A reviewer says "the access has started, so I can update PADDR for the next transfer." In two sentences, refute it and name which signal is the only one allowed to change after SETUP and why.
5. Generate PREADY/PSLVERR. Sketch (in words or RTL) a registered subordinate fronting a 4-cycle-latency block that can error, and state the three contract facts your design must honour: PREADY low during all waits, PREADY high for exactly the completion cycle, and PSLVERR valid only on that completion edge.

10. Key takeaways

• Every intermediate question is a stress test of one of two anchors — the two-phase stability contract or the completion handshake. Name the stress (extension, failure, streaming, stability) and the anchor, and the precise answer follows.
• The subordinate owns transfer length; the manager owns the start and the timeout. Wait states are unbounded by the protocol — the manager's only defence against an infinite wait is a watchdog that raises a bus error.
• Everything that terminates a transfer is sampled on one edge. PREADY, PRDATA, and PSLVERR are all evaluated on the completion edge and are meaningless off it — a PSLVERR pulsed during a wait cycle is invisible.
• Stability covers more signals than people remember. PADDR, PWRITE, PWDATA, PSTRB, and PPROT are frozen from SETUP through completion; PENABLE is the only control signal that changes, because it is the phase marker.
• PSTRB is write-only byte strobes; PPROT is the security/privilege handoff. Neither gates reads; both are part of the frozen access-defining set and PPROT violations surface as PSLVERR.
• Throughput is 1 / (2 + w) completions per cycle. The mandatory SETUP cycle caps a zero-wait back-to-back stream at 50% utilisation, and each wait state adds exactly one cycle — which is why APB stays a control-plane bus.