AMBA APB · Module 2

The Access Phase

The ACCESS phase — PENABLE high, the subordinate completing with PREADY high or stretching with PREADY low, and the rule that read data is valid and a write is accepted only at completion.

The SETUP phase presented the access; the ACCESS phase is where the access is actually performed and finished. It is the phase that carries the one moment every APB transfer is built around — the cycle on which a write is accepted and read data becomes valid. The trap to avoid: ACCESS is not a single cycle you can count on. It is elastic — it lasts as long as the subordinate needs, and exactly one of its cycles is the completion. The single idea to carry: a transfer is complete only when the lifecycle says so, and in ACCESS that "say-so" is PREADY going high — never a cycle sooner.

1. What problem is being solved?

The problem is performing the access and agreeing, unambiguously, on the one cycle it finishes — even when the subordinate cannot answer immediately.

SETUP did the preparation: the target is selected, the address and control are presented, and the subordinate has had a cycle to decode. But preparation is not the access. Something still has to commit — capture the write data into a register, or drive the requested read data back — and both the manager and the subordinate must agree on exactly when that happens. The complication is that subordinates differ in speed: a fast register answers at once, while a slow register or a clock-crossing bridge needs a few cycles. ACCESS solves both problems at once. It is the phase where the access is performed, marked by PENABLE high, and it is held — by PREADY — until the subordinate is ready, so that completion lands on one well-defined cycle whether the access takes one cycle or ten.

2. Why the previous mental model is not enough

The transfer overview treated ACCESS as a single step — present, then access, done. That is a useful first sketch, but it hides the property that causes most APB bugs: ACCESS is elastic, and exactly one of its cycles commits the data.

If you carry "ACCESS is the second cycle and that is where it finishes," you will read waveforms wrong the moment a subordinate inserts a wait. ACCESS is not "the cycle after SETUP"; it is a phase the transfer sits in — PENABLE high the whole time — that lasts until PREADY is high. Two things the single-step picture cannot express, but ACCESS must:

ACCESS can last many cycles. While the subordinate holds PREADY low, the access is held — a wait state. PENABLE stays high, the address and data stay stable, and nothing commits. The phase stretches; the lifecycle's shape does not.
Exactly one cycle is completion. Of all the cycles ACCESS spans, only the one where PREADY is high commits the data. Mis-reading which cycle commits — sampling read data a cycle early, or assuming the write landed before PREADY — is the classic APB bug. The whole point of this phase is to make that cycle unmistakable.

3. APB transfer mental model

The model: ACCESS is the handshake at the counter — you have handed over the form, and the transaction only counts when the clerk stamps it.

You have already filled in the form and slid it across (that was SETUP). Now you are standing at the counter with PENABLE high, waiting for the stamp. The clerk (the subordinate) controls the stamp: if they are ready, they stamp immediately and you are done in one cycle; if they are busy, they make you wait — you keep the form on the counter, nothing changes hands, and you wait until the stamp comes down. That stamp is PREADY high, and it is the only moment the transaction is real.

Three refinements make the model precise — and notice none of them is a deep dive into a signal; each is a lifecycle role:

PENABLE marks the phase, not the finish. PENABLE high means "we are in ACCESS, performing the access" — it is true for every cycle of the phase, including the wait cycles. It does not mean "done."
PREADY is the completion-and-backpressure control. The subordinate drives PREADY: high to complete, low to hold. It is the subordinate's one lever over timing — its way of saying "not yet" (backpressure) or "now" (completion).
The data commits on the stamp, and only then. A write is captured and read data is valid on the single cycle where PENABLE and PREADY are both high. Before that, the form is on the counter but the transaction has not happened.

Figure 1 — the ACCESS phase in two cases against PCLK, with PENABLE high throughout ACCESS in both. Top (immediate completion): after one SETUP cycle, ACCESS lasts a single cycle because the subordinate drives PREADY high straight away — the dashed marker is the completion edge. Bottom (stretched): after SETUP, ACCESS spans three cycles with PENABLE held high; the subordinate holds PREADY low for the first two (the wait states, where the access is held and nothing commits) and asserts PREADY high on the third, where completion lands. The phase changes length; its shape does not — exactly one cycle, where PREADY is high, completes the transfer.

4. Real SoC / hardware context

In hardware, ACCESS is the phase where the subordinate finally does something. On the manager side it is one state of the lifecycle FSM — PENABLE asserted, the manager sampling PREADY each cycle. On the subordinate side it is where the real work happens: a write enable is generated, a register is clocked, or a read mux drives PRDATA back. The subordinate decides how long it takes by holding or releasing PREADY.

Why does APB need this elasticity at all? Because a single APB bus hosts subordinates of wildly different speeds. A plain configuration register answers in its first ACCESS cycle. A register that lives in a slower clock domain, or behind a bridge to another bus, may need several cycles before its value is settled and safe to commit — so it holds PREADY low until it is, inserting wait states. The control plane does not care about the extra cycles (the traffic is rare and latency-insensitive, per why APB exists), so trading a few cycles for the freedom to host any-speed subordinate is exactly the right deal.

The whole of ACCESS reduces, in RTL terms, to one completion condition that everything keys off:

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Snippet

// APB ACCESS-phase completion condition (teaching sketch — not a full slave).
// True on exactly ONE cycle per transfer: the access is being performed
// (psel & penable, i.e. we are in ACCESS) AND the subordinate is ready.
wire access_done = psel & penable & pready;
 
// Commit ONLY when access_done is high:
//   - a write is captured here (sample PWDATA into the register)
//   - read data is sampled here (PRDATA is valid this cycle)
// While pready is low, access_done is low: the access is HELD (a wait state),
// PENABLE stays high, address/control/PWDATA are held stable, and NOTHING
// commits. The transfer is not done until access_done pulses high.

That one wire is the lifecycle marker made concrete. It is low for every SETUP cycle (PENABLE low) and for every wait cycle (PREADY low), and high for the single completion cycle. Anchor every commit in the design — the register write, the read sample, the manager's move to the next transfer — to that pulse, and the elasticity of ACCESS takes care of itself.

Figure 2 — the single completion point of the ACCESS phase. Before completion the access is in flight: PWDATA is being presented but not yet captured, and PRDATA is not yet valid to sample. Only on the completion edge — PENABLE high and PREADY high — is a write actually accepted into the register and read data actually valid. Reading PRDATA, or assuming a write committed, on any earlier ACCESS cycle is the classic APB bug; there is exactly one cycle where the data commits.

5. Engineering tradeoff table

ACCESS being a held, ready-gated phase is a deliberate choice. It costs predictability and buys universality — exactly the trade the control plane wants.

ACCESS design choice	What it gives up	What it buys	Why it is correct for APB
Held until `PREADY` (elastic length)	Fixed, known timing	Subordinates of any speed on one bus	Slow registers and clock-crossing bridges must be able to stall
`PENABLE` marks the phase, `PREADY` the finish	A single "done" signal	A clear split: phase vs completion	Lets the manager know it is in ACCESS yet still wait for the answer
Single completion cycle	Nothing real	One unambiguous commit edge	Removes all sample-timing guesswork in RTL and verification
Hold everything stable while waiting	Freedom to change mid-access	A safe, repeatable access for slow subordinates	Changing address or data mid-ACCESS would corrupt the transfer
Subordinate owns the timing (via `PREADY`)	Manager-side control of duration	Trivial, uniform manager logic	The subordinate is the only block that knows when it is ready

The throughline: ACCESS spends certainty about duration to buy certainty about completion. You do not know how many cycles ACCESS will take, but you know — exactly — the one cycle on which it finishes. For a control plane, that second certainty is the one that matters.

6. Common RTL / architecture / waveform mistakes

Misconceptions to unlearn

"PENABLE high means the access is done." No. PENABLE high means you are in ACCESS — it is true on wait cycles too. Completion is PENABLE and PREADY both high.
"ACCESS is always one cycle." No. ACCESS is held while PREADY is low, so it is one or more cycles. A fast subordinate completes in the first; a slow one stretches it.
"Read data is valid as soon as PENABLE goes high." No. PRDATA is valid only on the completion cycle (PREADY high). Sampling it during a wait state reads stale or undefined data.
"A write lands when the address appears, or at the start of ACCESS." No. A write is accepted only at completion. Until PREADY is high, PWDATA is presented but not committed.
"During a wait state the manager can change the address or data." No. While PREADY is low the manager must hold PSEL, PENABLE, address, control, and write data stable. Changing them mid-ACCESS corrupts the access.
"PREADY is just a status flag I can ignore for a fast register." No. Even a register that is always ready must complete through PREADY high. Completion is defined by the handshake, not by assuming readiness.

7. Interview framing

ACCESS is where an interviewer checks whether you actually know when an APB transfer commits. The give-away weak answer is "the access happens in the second cycle." The strong answer treats ACCESS as an elastic phase with one completion point.

Say it in three moves: ACCESS is marked by PENABLE high and is held until PREADY is high; the subordinate uses PREADY to complete (high) or insert wait states (low) — that is backpressure; and the data commits on exactly one cycle — PENABLE and PREADY both high — where a write is captured and read data is valid. Then volunteer the depth point that separates levels: while PREADY is low the manager holds everything stable and simply waits, so ACCESS changes length but never shape. What the interviewer is really probing is whether you locate the completion cycle correctly and understand that PENABLE marks the phase while PREADY marks the finish — the exact distinction that lets you debug a stretched APB waveform.

8. Q&A

9. Practice

Mark the completion. Given a waveform where ACCESS spans three cycles, identify which cycle is the completion and explain how you found it (PENABLE and PREADY both high).
Write the condition. From memory, write the one-line completion condition for ACCESS and state what must be gated on it (write capture, read sample).
Trace a wait state. For a read whose subordinate inserts two wait states, describe what is true on each ACCESS cycle — the value of PENABLE, of PREADY, and whether PRDATA is valid yet.
Spot the bug. A subordinate captures PWDATA on the first cycle PENABLE is high, regardless of PREADY. Explain, using the completion point, what goes wrong when that subordinate also inserts a wait state.
Defend the elasticity. In two sentences, justify why ACCESS being held by PREADY is the right design for a bus that hosts both a fast register and a clock-crossing bridge on the same wires.

10. Key takeaways

ACCESS is the phase where the access is performed and completed, marked by PENABLE high — true on every cycle of the phase, including wait states.
PREADY is the completion-and-backpressure control: the subordinate drives it high to complete or holds it low to insert wait states, stretching ACCESS without changing the lifecycle's shape.
ACCESS is elastic — one or more cycles — but exactly one of them is the completion: the cycle where PENABLE and PREADY are both high.
Data commits only at completion. A write is accepted, and read data (PRDATA) is valid, only on that single cycle — never on an earlier ACCESS cycle.
A transfer is complete only when the lifecycle says so, never when the address merely appears or when PENABLE first goes high. Gate every commit on psel & penable & pready.
The trade is duration for certainty: you cannot predict how long ACCESS lasts, but you know exactly the one cycle it finishes — and that certainty is what the control plane is built on.