Throughput

This chapter begins with what it will not claim, because the refusals are load-bearing.

APB's SETUP phase costs one clock per transfer. What that is worth depends entirely on how long the slave takes — and one number cannot express it.

1. The Refusal List

No synthesis tool was run on any RTL in this module. No place-and-route, no timing analysis, no library, no netlist. The following therefore appear nowhere in Module 21:

What can be counted, and is:

2. One Workload, Two Masters, No Room To Cheat

A protocol comparison is worthless unless both sides do identical work. Here that is guaranteed structurally rather than by care: there is one wl_workload instance per rig pair and both masters index into it.

// ─────────────────────────────────────────────────────────────────────────
// wl_workload — ONE workload, read by both protocol rigs.
//
// This module exists to make a comparison honest. The methodological
// failure that would ruin Module 20 is comparing a Wishbone system to an
// AXI system doing different work, and the cheapest way to make that
// impossible is to have exactly one description of the work and let both
// masters read it.
//
// There is ONE INSTANCE of this module in every comparison testbench. The
// Wishbone master and the AXI master each have their own index port into
// it. They cannot diverge, because there is nothing to diverge from.

Sixteen records — nine reads, seven writes, three of them sub-word so the byte-strobe path is exercised on both buses.

The slaves are the same memory too. apb_slave holds the same array, initialised to the same pattern, with the same byte-lane rule and the same wait-state parameter as the Wishbone RAM reused unchanged from Chapter 16.4:

// FAIRNESS IS THE POINT OF THIS MODULE. It holds the same array,
// initialised to the same pattern, with the same byte-lane write rule and
// the same wait-state parameter as the Wishbone RAM reused unchanged from
// Chapter 16.4. The ONLY difference between this slave and that one is the
// protocol on its pins.
//
//   mem[k] = 0xAAAA_0000 + k          identical to wb_shared_ram
//   byte lanes written per strobe      identical to wb_shared_ram
//   WAITS extra clocks before answer   identical to wb_shared_ram
//
// SIM A proves the equivalence by counting clocks on each side rather than
// asserting it here.

3. Zero Wait States

  === SIM E - ZERO wait states ===
      measure                     Wishbone   APB
        transfers                     16        16
        clocks transferring           16        32
        clocks per transfer          1.00       2.00
        APB SETUP clocks               -        16
        SETUP as % of APB clocks       -        50%

      ratio APB : Wishbone         2.00
      -> half of every APB clock at this setting is SETUP.
         The Wishbone RAM answers combinationally, which
         PERMISSION 3.10 allows, so it has no equivalent.

Two clocks against one, and half of every APB clock is SETUP.

This is APB's worst case and it is worth being precise about why: with a slave that can answer immediately, the SETUP phase is pure overhead, because the thing it exists to guarantee — stable, decoded address and control for a full cycle before anything acts — is a guarantee this particular slave did not need.

4. One Wait State

  === SIM F - ONE wait state ===
      measure                     Wishbone   APB
        clocks per transfer          2.00       3.00
        APB SETUP clocks               -        16
        SETUP as % of APB clocks       -        33%

      ratio APB : Wishbone         1.50

  === SIM G - FOUR wait states ===
      measure                     Wishbone   APB
        clocks per transfer          5.00       6.00
        APB SETUP clocks               -        16

Three clocks against two. The gap is still exactly one clock; the ratio has fallen from 2.00 to 1.50.

5. Four Wait States, And The Shape Of The Answer

      ratio APB : Wishbone         1.20

  === THE TREND - E, F and G together ===

      waits   Wishbone clk/xfer   APB clk/xfer   ratio
        0          1.00               2.00          2.00
        1          2.00               3.00          1.50
        4          5.00               6.00          1.20

      absolute gap, APB minus Wishbone, clocks per transfer
        0 waits  1.00    1 wait  1.00    4 waits  1.00

      THE RATIO NARROWS MONOTONICALLY: 2.00, 1.50, 1.20.

      That is the shape a FIXED OVERHEAD produces. APB's
      SETUP clock costs the same one clock whatever the
      slave does, so as the slave gets slower the same
      clock becomes a smaller fraction of the total.

      Note what did NOT happen: the sign never reversed.
      Chapter 20.3 compared Wishbone with AXI and the
      faster bus CHANGED between two slave latencies,
      because there the difference was structural on both
      sides. Here one bus has a constant extra clock and
      keeps it at every setting. Same method, different
      shape, and the shape is the finding.

      the absolute gap is the number that does NOT move:
      one clock per transfer at every wait-state setting,
      which is the SETUP phase and nothing else.

The shape is different from Module 20's, and the difference is the point

Chapter 20.3 ran the same method against AXI and found something else entirely: the sign of the difference reversed. Wishbone was ahead by 2 clocks with fast slaves and behind by 33 with slow ones, because there both protocols had structural properties that dominated at different latencies.

Here nothing reverses. One bus carries a constant extra clock and carries it at every setting. Wishbone is ahead at 0, 1 and 4 wait states — by 2.00×, then 1.50×, then 1.20×.

Same method, three data points instead of two, and a completely different curve. That is why §7's instruction was three settings rather than two: two points can show a difference but cannot show a shape, and here the shape is the whole result.

6. Where The Clocks Actually Go

SIM J breaks APB's clocks into phases at all three settings.

    3. THE PHASE BREAKDOWN, APB ONLY
       waits  transfers  SETUP  ACCESS  waits  min  max
         0        16       16      16      0     2    2
         1        16       16      32      16     3    3
         4        16       16      80      64     6    6
       -> SETUP is 16 at every setting. It is a constant,
          not a function of the slave.

    4. CLOCKS PER TRANSFER, BOTH BUSES
       waits   Wishbone    APB     gap     ratio

Read the SETUP column down: 16, 16, 16. It does not respond to the slave at all, because the slave is not consulted during SETUP. Everything that does respond to the slave is in the ACCESS column, which grows 16 → 32 → 80.

And read min and max: 2, 3, 6 — identical to each other at every setting. Every transfer in every run cost exactly the same, because this workload has no variation for the protocol to respond to. If the floor were not real, some transfer somewhere would come in below it. None ever does.

7. How Each Bus Stalls, And Why It Matters To The Trend

Both slaves take their wait states the same way in spirit and in a subtly different place, and that place is why the SETUP clock never joins the wait count.

The Wishbone RAM:

  logic xfer, ready;
  assign xfer  = cyc_i && stb_i;
  assign ready = xfer && (held_q >= WAITS[7:0]);

  assign ack_o    = ready && !busy_i;
  assign rty_o    = xfer  &&  busy_i;
  assign err_o    = 1'b0;

xfer is the request existing; ready is the request having waited long enough. The counter starts the moment the request appears, because on Wishbone the request appearing and the request being presented to the slave are the same event.

The APB slave:

  logic in_setup, in_access;
  assign in_setup  = psel_i && !penable_i;
  assign in_access = psel_i &&  penable_i;

  assign pready_o  = in_access && (held_q >= WAITS[7:0]);
  assign pslverr_o = pready_o && (paddr_i[7:0] > ERR_ABOVE);

Note pready_o: it is gated by in_access, not by in_setup. And the counter:

      // the wait counter runs only inside ACCESS - SETUP is not waitable
      if (in_access && !pready_o) held_q <= held_q + 8'd1;
      else                        held_q <= 8'd0;

The wait counter runs only inside ACCESS. A slave cannot start waiting during SETUP, because it has not been asked anything yet — PREADY is not sampled until PENABLE is high.

8. Where The Clocks Go, Per Transfer

Putting §3–§6 into one table, per single transfer:

Every row is the same except the first two, and those two are one row on Wishbone and two on APB. That is the entire measurable content of this chapter, and the three data points in §5 are that formula evaluated at W = 0, 1 and 4.

The formula also tells you where APB stops mattering. At W = 0 the overhead is 100%. At W = 9 it would be 10%. There is no wait-state setting at which APB becomes faster, and none at which the absolute cost is more than one clock.

9. What Neither Bus Does

Neither pipelines, and both say so.

• APB, §1.1: "The APB protocol is not pipelined"
• Wishbone, RULE 3.35: the termination signals "must be generated in response to the logical AND of [CYC_I] and [STB_I]" — the answer belongs to the one request on the wires, so there cannot be a second

So this is not a comparison of a fast bus with a slow one. It is two single-transfer buses with different floors, and the entire measurable difference is one clock that one of them spends before starting.

Chapter 20.3's AXI rig reached four outstanding transactions and saved 33 clocks on this same workload. Neither bus in Module 21 can reach two. That is the axis on which these two are alike and AXI is different — and it is why the honest summary of this chapter is "one clock" rather than "a protocol generation apart".

10. The Summary Worth Keeping

Three readings, all true:

• With a slave that answers immediately, APB does half the work per clock.
• With a slave that takes five clocks, APB does 83% of it.
• At every setting, APB costs exactly one more clock per transfer and never more.

The protocol did not decide any of those. The slave latency did.