Build engineering skill by doing the work
Hands-on RTL design and verification labs — Verilog, SystemVerilog and VHDL through UVM, GLS and DFT. Write the code, run a self-checking testbench, read the waveform, and debug what the simulator actually did.
Tutorials stay free · Lab packs are paid, hands-on practice
01Core HDL & RTL
Build the language and RTL reasoning foundation — what the code means before how it is written.
Verilog HDL Labs
Explained Verilog RTL, self-checking testbenches, waveform guidance and challenges — gates through to full projects.
SystemVerilog Labs
RTL constructs through assertions, classes, constrained random and coverage, ending in verification projects.
VHDL Design & Simulation Labs
VHDL-2008 from gates and counters through FSMs, memories, UART, SPI and CDC, ending in automated regression.
RTL Design Patterns Labs
Advanced SystemVerilog RTL — arbiters, pipelines, async FIFOs, DMA-style control, SRAM and SECDED.
02Verification
Develop systematic verification and silicon sign-off reasoning, from methodology to gate level.
UVM Verification Labs
UVM from a first testbench to sign-off — agents, sequences, the factory, scoreboards, coverage, APB/AHB/AXI environments and debugging.
UVM RAL Verification Labs
Register Abstraction Layer verification over APB — register models, adapters, prediction, access policies, side effects and RAL debugging. All labs are published.
Gate-Level Simulation (GLS) Lab
RTL-to-gate-level verification — netlist simulation, X propagation, SDF annotation, setup and hold violations, and GLS signoff.
DFT Design & Verification Labs
Design for Testability in RTL — stuck-at faults, scan chains, fault simulation and ATPG concepts, MBIST, logic BIST, JTAG and integration verification.