Wishbone tutorials, labs & MCQs.
The most complete Wishbone curriculum on the internet — from first principles (why on-chip buses exist, memory-mapped IO, open-source SoC and FPGA interconnect) before signal descriptions, then through the architecture, the CYC/STB/ACK handshake, read/write/block/RMW cycles, wait states, error and retry, address decoding, byte selects, multi-master arbitration, interconnect design, RISC-V/LiteX integration, AXI/APB comparisons, performance, RTL design, DMA, verification, debugging, and interview mastery.
Tutorials
Learn Wishbone from beginner to advanced through structured tutorials.
Labs
Practice Wishbone using progressively challenging hands-on labs.
MCQs
No MCQ papers for Wishbone yet.
What Wishbone is
Wishbone is an open, royalty-free specification for connecting blocks inside a single chip. It defines a small synchronous interface — an address, two unidirectional data paths, a write-enable, byte selects, and a handshake in which a master asserts a request and a slave answers it — and a set of bus cycles built from that interface. What it deliberately does not define is the fabric: the specification describes the interface a portable IP core presents, and leaves the topology connecting those cores to the integrator, so the same slave can sit on a point-to-point link, a shared bus or a crossbar without changing. It came out of the open-hardware world rather than a vendor, and it is the interconnect most commonly found in OpenCores IP and in open-source RISC-V and FPGA SoCs.
Why it exists
A processor core is useless on its own: the work a system actually does happens in peripherals — a UART, a timer, a GPIO block, a memory controller — and the CPU can only reach them by reading and writing. Wiring each peripheral to the core with its own private signals works for two blocks and collapses for twenty, because every new block changes the core. A bus fixes one interface so that a peripheral can be designed, verified and reused without knowing what else is in the system. Wishbone's particular contribution is that this interface is free to use and small enough to implement in a few dozen lines of RTL, which is why an open-hardware ecosystem could standardise on it at all.
The part engineers get wrong
The most useful habit to build early is separating what the specification fixes from what the integrator chooses. Wishbone fixes the signals a master and a slave exchange and the rules of the handshake between them; it does not fix the address map, the topology, the arbitration policy or how many wait states a slave may insert. That is why two Wishbone systems can look nothing alike and both be conformant, and why a bug is usually in the part nobody standardised — a decode range that overlaps, an arbiter that starves a master, a slave that never returns an acknowledgement. The second thing worth holding early is that the handshake is what makes a slave allowed to be slow: a transfer ends when the slave says it does, not after a fixed number of cycles, which is exactly what lets a fast core and a slow peripheral share one bus.
Before you start
- Digital design — synchronous logic, state machines and reset behaviour
- Basic RTL fluency in Verilog or SystemVerilog
- Helpful but not required: any prior exposure to an SoC, a register map or a device driver
What you will be able to do
- Explain why a CPU needs a defined mechanism to reach peripherals, and what a bus fixes that ad-hoc wiring does not
- Read a Wishbone interface signal by signal and say who drives each one
- Trace a read and a write cycle through the handshake, including wait states and error termination
- Design an address decoder and a read-data multiplexer for a set of slaves
- Reason about multi-master arbitration and what it costs
- Write a Wishbone master and slave in RTL, and debug a bus that has stalled
The learning path
- Why Wishbone existsCPU-to-peripheral communication, memory-mapped IO, and why an open interconnect standard was worth having
- On-chip bus fundamentalsMasters and slaves, address space, transfers and the vocabulary every bus shares
- Wishbone architectureThe master and slave interfaces, the interconnect, and the life of a transaction
- The signalsEvery signal in the interface — purpose, ownership, timing and the mistakes each one invites
- The handshake and the cyclesCYC/STB/ACK, read and write cycles, block transfers, wait states, error and retry
- Decoding and arbitrationTurning an address into a slave select, and sharing a bus between several masters
- Interconnect and integrationTopologies, RISC-V and FPGA SoCs, and how Wishbone compares with AXI and APB
- RTL, verification and debugBuilding masters, slaves and interconnect, verifying them, and reading a stalled bus
Core concepts
New to Wishbone? Work through the curriculum in order — each lesson assumes the one before it, and the sequence is what turns the roadmap above into working knowledge.
Already working with it? Use the core-concept links above to jump straight to the topic you need; each one opens the lesson that covers it in most depth.
Where this leads
Standards: OpenCores — Publishes the Wishbone SoC interconnection architecture specification