Design Trade-offs

// ── THE THREE THINGS IT HAS TO GET RIGHT ────────────────────────────────
//
// 1. THE BYTE LANES MUST SURVIVE.
//    Wishbone  "The array boundaries are determined by the granularity of
//               a port."                        (B3, DESC SEL_O)
//    AXI       "There is one write strobe for each 8 bits of the write
//               data bus, therefore WSTRB[n] corresponds to
//               WDATA[(8n)+7:(8n)]."            (IHI 0022H, A3.4)
//    The two definitions agree, so SEL_O maps to WSTRB one bit to one
//    bit. It is the easiest thing in this module to get right and the
//    easiest to leave out, because a bridge that drives WSTRB to all-ones
//    works perfectly for every full-word access.
//
// 2. THE TERMINATION MUST MEAN THE TRANSFER HAPPENED.
//    B3 RULE 3.35 makes [ACK_O] the answer to the request. If this bridge
//    asserts [ACK_O] before the AXI side has answered, the Wishbone master
//    is told a write committed that is still in flight - and on a READ it
//    is handed data that has not arrived. NOTHING IN B3 IS VIOLATED by
//    doing this: the bridge is a conformant slave that simply answers
//    early. The lie is in the meaning, not in the timing rules.
//
// 3. THE ERROR MUST SURVIVE TRANSLATION.
//    AXI's SLVERR is "Slave error... to the originating master"; Wishbone
//    has [ERR_O]. Mapping one to the other is arithmetic. Dropping it
//    turns a failed access into a successful one, which is Chapter 19.4's
//    ERR_SWALLOWED finding arriving at a different seam.
//

      answers           bridged 16   direct 16
      order signature   bridged 0x98b97cbd   direct 0x98b97cbd
      out-of-order      bridged 0   direct 0
      errors reported   bridged 0   direct 0

      EVERY VALUE AND EVERY ORDER IDENTICAL. A protocol
      translation sat in the middle of all 16 accesses and
      nothing the master could observe changed.

      bridge bookkeeping
        Wishbone requests forwarded to AXI   16
        answers returned to Wishbone         16
        non-OKAY responses seen              0
        AXI slave writes / reads             7 / 9

      clocks to finish   bridged 146   direct 82
      -> THE COST OF THE SEAM IS 64 CLOCKS over 16 accesses.
         And it cannot be recovered by making the AXI side
         deeper, because the Wishbone master supplies one
         request at a time. A bridge cannot use depth its
         other side cannot express - which is why Chapter
         20.5 argues the seam, not the bus, is the decision.

  === NEGATIVE-CONTROL GATE ===
    one stimulus set, seven systems. Each broken system
    differs from the correct one by exactly one parameter.

    checker                        corr STRB EARL RESP COUP BRST REORD
    WRITE STROBES SURVIVE          PASS FAIL PASS PASS PASS PASS PASS
    ONE RESPONSE PER REQUEST       PASS PASS FAIL PASS PASS PASS PASS
    ERROR SURVIVES TRANSLATION     PASS PASS FAIL FAIL PASS PASS PASS
    CHANNELS ARE INDEPENDENT       PASS PASS PASS PASS FAIL PASS PASS
    A BURST IS N TRANSFERS         PASS PASS PASS PASS PASS FAIL PASS
    RESPONSES MATCH THEIR REQUESTS PASS PASS PASS PASS PASS FAIL FAIL

    raw numbers behind those verdicts
      column          strb  early  errs  alone  beats  RID order
      correct          0      0      3     7      8    0x00005500
      STRB_DROP        4      0      3     7      8    0x00005500
      EARLY_ACK        0      16      0     7      8    0x00005500
      RESP_IGNORE      0      0      0     7      8    0x00005500
      AR_R_COUPLED     0      0      3     0      8    0x00005500
      BURST_AS_ONE     0      0      3     7      2    0x00000004
      REORDER          0      0      3     7      8    0x00000055

    CHECKERS REQUIRED:                >= 5
    CHECKERS DECLARED:                6
    CHECKERS PASSING THE CORRECT SYSTEM:                   6/6
    EACH CHECKER FAILS ITS OWN TARGET:
      6/6

    READ THE OFF-DIAGONAL. EARLY_ACK fails TWO checkers,
    and the second one is worth more than the first. A
    bridge that terminates the Wishbone cycle when the AXI
    request is ACCEPTED has already answered by the time the
    SLVERR arrives, so the error is not translated - it is
    not there to translate. Its error count is 0 against
    the correct system's 3. ONE WRONG DECISION ABOUT WHAT
    A TERMINATION MEANS SILENTLY DISABLED THE ENTIRE ERROR
    PATH, and nothing in either specification was violated.

    FIVE OF THESE SIX ARE LEGAL. A bridge that drops byte
    strobes, one that answers early, one that discards a
    SLVERR, a slave that collapses a burst, a slave that
    reorders across IDs - none of them violates Wishbone B3
    or IHI 0022H. They are all decisions somebody could
    defend in a review.

    AR_R_COUPLED IS THE EXCEPTION AND IT IS THE POINT.
    "VALID signal of the AXI interface sending information
     must not be dependent on the READY signal of the AXI
     interface receiving that information."   (A3.3.1)
    That defect breaks a rule, so a conformance checker
    finds it without knowing anything about this design.
    Across Modules 9-19 the count of published defects a
    bus-level protocol checker would catch stood at ONE.
    Module 20 adds the second.

    Note what it took: the defect is invisible unless the
    stimulus withholds RREADY. The correct column's "alone"
    count is 7 and the coupled column's is 0 - and if
    this testbench had left RREADY tied high, as both of
    this module's masters do, both numbers would be zero
    and the checker would have proved nothing.

  // ── GROUP 3: THE BRIDGE — owned by neither specification ─────────────
  //
  // Every property below is this design's own. There is no rule number to
  // put beside any of them, which is the whole reason Module 20 measures
  // the bridge rather than citing it.

  // The byte lanes must survive translation. SEL_O and WSTRB are defined
  // identically by the two specifications, so this is a wire, and it is
  // the easiest thing in the module to leave out.
  property p_strobes_survive;
    @(posedge clk_i)
      (wvalid_i && wready_i) |-> (wstrb_i == sel_i);
  endproperty
  a_strobes_survive: assert property (p_strobes_survive);