Integration Trade-offs

// side "APB bridge" rather than "master", which is the specification
// saying out loud that something is expected to sit here.
//
// ── DIRECTION IS A LOCAL POLICY AND IS STATED ───────────────────────────
// This bridge carries Wishbone requests to an APB slave. The other
// direction is not built and is NOT claimed.
//
// ── THE FOUR THINGS IT HAS TO GET RIGHT ─────────────────────────────────
//
// 1. EVERY TRANSFER GETS A SETUP PHASE.
//    "The bus only remains in the SETUP state for one clock cycle and
//     always moves to the ACCESS state on the next rising edge of the
//     clock."                              (ARM IHI 0024C, section 4.1)
//    A bridge that asserts PSEL and PENABLE together has not shortened
//    anything - it has produced a transfer the slave's state machine was
//    never defined for. NOTHING IN WISHBONE IS VIOLATED by doing this.
//
// 2. THE ACCESS PHASE IS HELD UNTIL PREADY.
//    "Exit from the ACCESS state is controlled by the PREADY signal from
//     the slave."                          (ARM IHI 0024C, section 4.1)
//    Dropping PENABLE early abandons a transfer the slave is still
//    performing. On a write that means the data may never be committed.
//
// 3. THE BYTE LANES MUST SURVIVE.
//    Wishbone  RULE 3.60 qualifies [SEL_O()] with [STB_O].
//    APB       "PSTRB A write strobe signal to enable sparse data
//               transfer on the write data bus."  (IHI 0024C, s1.2.3)
//    One bit to one bit. The easiest thing here to get right and the
//    easiest to leave out, because all-ones works for every full word.

      order signature   bridged 0x98b97cbd   direct 0x98b97cbd
      errors reported   bridged 0   direct 0

      EVERY VALUE AND EVERY ORDER IDENTICAL. A protocol
      translation sat in the middle of all 16 accesses and
      nothing the Wishbone master could observe changed.

      bridge bookkeeping
        Wishbone requests forwarded   16
        answers returned              16
        SETUP clocks driven           16
        ACCESS clocks driven          32
        ACCESS phases abandoned       0
        APB slave writes / reads      7 / 9
        -> exactly one SETUP per forwarded request.

        bridged  5.00      direct  2.00
      the seam costs 3.00 clocks per access. DO NOT
      ATTRIBUTE ALL OF THAT TO APB - decompose it:

        SETUP phases driven           16 clocks = 1.00/xfer
        everything else               32 clocks = 2.00/xfer

      ONLY THE FIRST ROW IS APB'S. It is the floor from
      section 4.1 and no bridge can remove it: the slave is
      not consulted during SETUP, so no slave can be fast
      enough to skip it.

      THE SECOND ROW IS THIS BRIDGE'S OWN. It registers the
      Wishbone request before driving PSEL, and its wait
      counter runs inside ACCESS where the Wishbone RAM's
      runs from the request. A bridge with combinational
      outputs would be faster and harder to time-close.
      Publishing the split is the difference between
      measuring a protocol and measuring one afternoon's
      RTL.

      What survives the decomposition: a bridge cannot be
      faster than the slower side of the seam. Module 20
      found depth that could not be used; here it is a
      floor that cannot be lowered.

  === errors: 0 ===

  === NEGATIVE-CONTROL GATE ===
    one workload, six systems. Each broken system differs
    from the correct one by exactly one parameter.

    checker                        corr NOSU EDRP STRB EIGN SACT
    EVERY TRANSFER HAS A SETUP     PASS FAIL PASS PASS PASS PASS
    ACCESS HELD UNTIL PREADY       PASS PASS FAIL PASS PASS PASS
    BYTE LANES SURVIVE             PASS PASS PASS FAIL PASS PASS
    ERROR SURVIVES TRANSLATION     PASS PASS FAIL PASS FAIL PASS
    SLAVE ACTS ONLY IN ACCESS      PASS PASS FAIL PASS PASS FAIL
    ONE TRANSFER PER REQUEST       PASS PASS PASS PASS PASS PASS

    CHECKERS REQUIRED:                >= 5
    CHECKERS DECLARED:                6
    CHECKERS PASSING THE CORRECT SYSTEM:      6/6
    EACH CHECKER FAILS ITS OWN TARGET:
      5/5 targeted defects detected

    READ THE OFF-DIAGONAL. EARLY_DROP FAILS THREE CHECKERS
    AND THE TWO IT WAS NOT AIMED AT ARE THE ALARMING ONES.

    Its slave write count is 0 against the correct
    system's 5, and its error count is 0 against 3.
    A bridge that drops PENABLE after one ACCESS clock,
    without waiting for PREADY, ends every transfer before
    the slave has committed anything. NOT ONE WRITE LANDED.
    NOT ONE ERROR WAS RAISED. And the Wishbone master was
    told all 16 accesses succeeded - fwd 16, answered 16.

    ONE WRONG DECISION ABOUT WHEN A PHASE MAY END SILENTLY
    DISABLED THE ENTIRE WRITE PATH AND THE ENTIRE ERROR
    PATH, and the bus it reported to saw nothing wrong.
    Chapter 20.5 found the same shape at an AXI seam with
    EARLY_ACK; this is worse, because there the data at

    WHICH OF THESE WOULD A CONFORMANCE CHECKER CATCH?
    NO_SETUP breaks a rule. Section 4.1 says the bus "only
    remains in the SETUP state for one clock cycle and
    always moves to the ACCESS state on the next rising
    edge of the clock" - a transfer with PENABLE high on
    the clock PSEL rose never occupied SETUP at all.

    EARLY_DROP breaks one too: "Exit from the ACCESS state
    is controlled by the PREADY signal from the slave", and
    s3.1.2 lists PENABLE among the signals that "remain
    unchanged while PREADY remains LOW".

    The other three do not. A bridge that drops byte
    strobes, one that discards PSLVERR, and a slave that
    acts on PSEL rather than PENABLE all produce perfectly
    legal waveforms. Nothing in IHI 0024C says WHEN a

  // Section 4.1 — "The bus only remains in the SETUP state for one clock
  // cycle and always moves to the ACCESS state on the next rising edge of
  // the clock." SETUP is PSEL without PENABLE, so a SETUP clock is always
  // followed by an ACCESS clock. This is the two-cycle floor, asserted.
  property p_setup_is_one_clock;
    @(posedge clk_i)
      (psel_i && !penable_i) |=> (psel_i && penable_i);
  endproperty
  a_setup_is_one_clock: assert property (p_setup_is_one_clock);

  // The corollary: PENABLE may not rise in the same clock PSEL rises.
  // A transfer that does has not occupied SETUP at all.
  property p_no_enable_without_setup;
    @(posedge clk_i)
      $rose(psel_i) |-> !penable_i;
  endproperty
  a_no_enable_without_setup: assert property (p_no_enable_without_setup);