Go deeper with structured video courses
Build deeper engineering understanding through focused video courses designed around real RTL, verification, protocol, and semiconductor workflows.
In production · Enrolment opens as each course ships
01Core HDL & RTL
Go beyond syntax with structured courses in RTL design, HDLs, and reusable design reasoning.
Verilog Video Course
Lab-paced Verilog RTL video walkthroughs — write the RTL, build the testbench, run the regression.
02How these courses are taught
A VLSI Mentor video course is a worked engineering session, not a narrated slide deck. The method is the one the written tutorials and the labs already use — it is stated here so you can judge it before anything is charged for.
Start from the problem, not the syntax
Every topic opens with the engineering problem that made the construct necessary — what breaks without it, and what the alternatives cost. Syntax is introduced once the problem makes it inevitable, which is what makes it stick.
Write the RTL on screen
Code is typed and explained line by line, not shown as a finished slide. That includes the parts that are usually skipped: reset strategy, width choices, and the sensitivity or driver rules that decide whether the block synthesises to what you intended.
Verify it, do not assert it works
Each design is exercised by a self-checking testbench rather than an eyeball on a waveform. The check is written before the result is trusted, so a passing run means something specific.
Read the waveform and the failure
Time is spent on what the simulator actually did — including deliberately broken variants. Recognising a race, an X-propagation, or a missed reset in a waveform is a skill that only transfers by watching it happen.
03Who these courses are for
The audience is the same one the rest of the platform is written for: engineering students and working silicon engineers who are short on time and want the reasoning, not a tour of the syntax.
Engineering students and recent graduates
You know the language well enough to pass a viva, but have not yet built a block, verified it, and debugged it end to end. The courses are paced to close that gap rather than to re-teach syntax.
Working engineers moving across the stack
Design engineers moving toward verification, or verification engineers who want to read RTL properly. The material assumes you are competent and short on time, and does not pad.
Engineers preparing for interviews
Interview questions in this field are mostly about reasoning — why a construct behaves as it does, and what fails when it is misused. That reasoning is the spine of the courses, not an appendix to them.
04How video courses relate to the free tutorials
The written tutorial library is free and stays free. A video course does not gate material that is already published, and it is not a recording of the same pages read aloud.
What a course adds is the part a written page cannot easily carry: watching a design get built and debugged in real time — the hesitation before a width is chosen, the run that fails, and the waveform being read until the reason is obvious. The written tutorials remain the reference you return to afterwards.
Nothing you learn from the free material is wasted if you later take a course, and no course is a prerequisite for any free tutorial.
05What to study while the courses are in production
Every surface below is live now. Working through them is the best preparation for a course, and is a complete path on its own.
Verilog tutorials
The full written Verilog curriculum — nets and variables through procedural blocks, FSMs, timing and testbench construction. Free.
Read the tutorialsSystemVerilog tutorials
RTL constructs through interfaces, classes, constrained random, assertions and functional coverage. Free.
Read the tutorialsHands-on labs
58 Verilog and 56 SystemVerilog labs, plus 6 projects — write the RTL, run a self-checking testbench, read the waveform. Paid lab packs.
Verilog labsSystemVerilog labsMCQ practice
Questions written around real concepts, failure modes and design decisions, with the reasoning explained in every answer.
Practice MCQs06Current status and what to expect
No video course has shipped yet. The courses listed above are in production, and each one appears here with its price the moment it is registered — we do not open enrolment on a course that does not exist.
When a course does ship, three things will be true. Its price is shown up front on this page. Enrolment runs through the same request-and-review flow the rest of the platform uses — payment is completed outside the website and access is granted to your account once it is verified, as set out in the Terms. And the free written tutorials covering the same subject stay free.
We do not publish release dates for material that is still being recorded, and there is no waiting list to join.
Available today
Browse every track — Verilog, SystemVerilog, VHDL, UVM and the protocol curricula — from the library index. Learnings