Throughput Improvements

Chapter 14.1 measured four words in 8 clocks as separate cycles and 5 as one block.

That is one number under one set of conditions, and quoting it as "block transfers are 1.6× faster" would be the exact failure this chapter exists to prevent.

What does grouping actually buy, and what does it leave completely untouched?

1. Define the Metrics Before Measuring

Every number below is one of these, and none of them is "bandwidth" unless a frequency is stated.

"Clocks per word" is the useful one because it is independent of N and can be compared across runs — the same measure Chapter 8.6 used for single cycles.

Bandwidth needs two more facts. At DW = 32 bits and a clock frequency f, payload throughput is 32 × f / (clocks per word) bits per second. This module never states f, so it never states a bandwidth — the clock-domain choice belongs to a system, and Module 22 is where performance analysis becomes the subject.

2. Where the Saving Comes From

A separate cycle per transfer pays a boundary per transfer. CYC_O falls after one transfer and rises before the next, and those clocks move no data.

For N transfers in one cycle there are N − 1 boundaries avoided. That is the entire mechanism, and it predicts a constant saving — not a proportional one.

Which means the ratio depends on what the transfers themselves cost. Cheap transfers make the constant look large; expensive ones make it vanish. Sections 4 and 5 measure both ends of that.

3. RTL — Nothing New

The master, the RAM and the probe are Chapter 14.1's, unchanged. BLOCK selects the grouping, WAITS sets the slave's latency, and GAP makes the master pause. Three parameters over one design is what makes the table below a measurement of those parameters rather than a comparison of three programs.

The slave's latency mechanism is the specification's, and it is Module 9's subject unchanged: it withholds its termination. The BLOCK READ text says "SLAVE negates ACK_I to introduce a wait state", and held_q in the RAM counts the clocks a phase has gone unanswered.

The master's is also the specification's: "MASTER negates STB_O to introduce a wait state (-WSM-)", which is what GAP does — and with BLOCK set, CYC_O is retained through it, exactly as the normative figure shows.

4. Simulation — SIM C: The Same Work at Three Latencies

Four transfers, six rigs. Both groupings against a slave that answers immediately, after one wait state, and after three.

  === SIM C - the same work at three slave latencies ===
    4 transfers, 32-bit words. 'clocks' is from the client's
    start to the master's done pulse.

    grouping   slave waits  cycles  phases  clocks  clk/word
    separate        0        4       4       8    2.00
    separate        1        4       4      12    3.00
    separate        3        4       4      20    5.00
    block           0        1       4       5    1.25
    block           1        1       4       9    2.25
    block           3        1       4      17    4.25

    Read the two zero-wait rows against each other, then the
    two three-wait rows. The saving from grouping is a fixed
    number of clocks, and the slave's latency is multiplied by
    the transfer count in both groupings.

Reading it — subtract the columns, do not divide them

Take the difference in each latency pair:

The difference is three in every row. Three is N − 1 for four transfers — one clock per avoided cycle boundary, exactly as Section 2 predicted, and completely independent of how long the slave takes.

The ratio is not constant and is not a property of block transfers. It falls from 1.60 to 1.18 across the same table, with nothing in either design changing. Only the slave got slower.

Now read down the latency column instead. Each wait state adds 4 clocks in both groupings — one per transfer, because there are four transfers and each pays the latency separately. Slave latency is multiplied by N; the grouping saving is not.

5. What Grouping Cannot Touch

Run the arithmetic on the three-wait rows. Twenty clocks for four transfers as separate cycles; seventeen as a block. Of the seventeen, twelve are the slave waiting — four transfers × three wait states.

The grouping removed three clocks from a total in which twelve were latency. No amount of restructuring the cycle boundaries touches those twelve, because they are the slave withholding its termination and the master has no say in it.

This is the practical ceiling of the technique. Grouping is worth a fixed, small number of clocks. When transfers are cheap that is a large fraction; when they are not, it rounds to nothing — and the second case is the common one for real memory.

The specification anticipates exactly this. OBSERVATION 3.50 notes that registering the termination signals — which large designs need, to cut the loopback delay from master to slave and back — costs "one additional wait state per transfer", and points at WISHBONE Registered Feedback Bus Cycles for methods of eliminating the wait state. That is a different profile, and Chapter 14.3 names it.

6. Simulation — SIM D: Gaps the Master Chose

The same block, the same zero-wait RAM, and a master that negates STB_O for two clocks after each phase — the specification's own master wait-state mechanism, used where nothing required it.

  === SIM D - a block cycle with gaps the master chose ===
    same block, same zero-wait RAM, master negates STB_O for
    two clocks after each phase - the specification's own
    master wait-state mechanism, used where nothing needed it.

    master        cycles  phases  clocks  idle clocks  written
    back-to-back       1       4       5            0        4
    with gaps          1       4      11            6        4

    Identical memory contents, identical transfer count, and
    one takes longer. Correctness and throughput are separate
    properties and nothing on the bus reports the difference.

Reading it

Identical memory contents. Identical transfer count. Identical cycle count. Eleven clocks against five.

Six idle clocks — two after each of the three non-final phases — during which CYC_O stayed asserted and nothing was presented. The gapped master still holds the resource for every one of them, which is the part an arbiter cares about.

And the bus reports nothing. Both runs are protocol-correct: CYC_O retained, STB_O negated by the master, which is precisely how the specification says a master inserts a wait state. A conformance checker sees two conforming masters.

The evidence that separates them is the interval between a termination and the next presentation. Zero in one, two in the other. That is the measurement to reach for when memory is right and a block is slow — and it is a master-side measurement, not a slave-side one.

Which is the general lesson under it: correctness and throughput are independent properties. A design can be exactly right and needlessly slow, and nothing in the protocol will tell you.

G holds CYC_O throughout and presents on one clock in three. Over the full run measured in SIM D that is eleven clocks of tenure for five of work. Every clock where CYC_O is high and STB_O is low is tenure without work — and CYC_O is the signal the specification says an arbiter watches.

Both rows are conformant. Negating STB_O under a retained CYC_O is the specification's master wait-state mechanism. Nothing here is a protocol violation; it is an occupancy problem.

7. Back-to-Back Is Not Pipelined

These two phrases describe different mechanisms and the difference is not one of degree.

Back-to-back means no idle clock between one phase's termination and the next phase's presentation. SIM C's block rows are back-to-back, and the specification confirms the ceiling: "The BLOCK cycle is capable of a data transfer on every clock cycle."

Pipelined means a second request is issued before the first response arrives — multiple outstanding transfers. In Classic Wishbone there is no such thing. The BLOCK READ sequence latches each phase's data at the edge that ends it, and presents the next address at that same edge. One transfer is in flight at a time, always.

The ceiling is the clean way to tell them apart. One transfer per clock is the best a back-to-back non-pipelined bus can do, and SIM C's zero-wait block reaches 1.25 clocks per word — close to it, with the extra quarter being the cycle's own start and finish.

Calling Classic "pipelined" because it can do a word per clock is a category error. The word describes a structure, not a rate, and a system built on that assumption would expect latency to overlap when it cannot.

8. Failure Modes and Discriminating Evidence

Symptom: memory contents are correct and the block takes far longer than expected.

Candidate causes. A master inserting gaps, an unnecessary CYC_O drop between transfers, or slave latency that was not budgeted for.

Discriminating evidence. The interval from each termination to the next presentation, and the cycle count. A non-zero interval is a master gap. A cycle count equal to the transfer count means the grouping never happened. Neither is visible in the data, which is why this symptom arrives as "it works but it's slow".

Symptom: a measured speedup does not reproduce on different hardware.

Candidate causes. The original figure was measured against a faster slave.

Discriminating evidence. Recompute the saving in clocks rather than as a ratio. If it is still N − 1, nothing regressed — the denominator changed. SIM C is this experiment, and its three rows have one difference and three ratios.

Symptom: adding transfers to a block does not improve clocks per word.

Candidate causes. Slave latency dominates, so the amortised boundary saving is already negligible.

Discriminating evidence. Wait clocks as a fraction of presenting clocks. At three wait states, twelve of seventeen clocks are the slave. Longer blocks amortise a constant that is already small — the fix is on the slave side or in a different profile.

Symptom: throughput is below one word per clock even with a zero-wait slave.

Candidate causes. Cycle start and finish overhead, or a master that cannot present on consecutive clocks.

Discriminating evidence. Presenting clocks against transfer count. Four presenting clocks for four transfers means the phases themselves are at the ceiling and the remainder is the cycle's ends. More than four means the master is not back-to-back, whatever CYC_O is doing.

9. Common Mistakes

"Block transfers are faster."

Wrong mental model: a property of the mechanism.

What is true: grouping saves N − 1 clocks. Whether that is 60% or 18% depends entirely on what a transfer costs — both figures are in SIM C, from the same two designs.

"Keeping CYC_O high gets you one word per clock."

Wrong mental model: grouping sets the rate.

What is true: the slave sets the rate. At three wait states the block managed 4.25 clocks per word. CYC_O never touched the twelve clocks the slave spent.

"More throughput means more than one word is moving at a time."

Wrong mental model: rate implies width or overlap.

What is true: the improvement here is entirely the removal of idle overhead, one transfer at a time throughout. Nothing was widened and nothing overlapped.

"Back-to-back means pipelined."

Wrong mental model: synonyms.

What is true: back-to-back is about gaps; pipelined is about outstanding requests. Classic has the first and not the second, and conflating them predicts latency hiding that cannot happen.

"A longer block is always better."

Wrong mental model: the saving scales.

What is true: the saving is one clock per avoided boundary and the latency cost is per transfer. Beyond a point the clocks-per-word curve flattens at the slave's latency plus one, and more transfers buy proportionally less.

10. Interview Reasoning

11. Understanding Check

12. What's Next

Throughput is quantified: a constant saving, a multiplied latency, and a ratio that means nothing without its conditions.

Four transfers under one cycle, with addresses that happened to increment. Nothing so far has said they had to.

If the slave is never told the length, the order, or when the block ends — in what sense is this a burst at all?

Chapter 14.3 — Burst-Like Behavior runs a legal block whose addresses go backwards, and names the B3 profile where burst metadata actually exists. The full path is on the Wishbone curriculum index.