CXL tutorials & labs.
The most complete CXL curriculum on the internet — starting from the memory-wall and accelerator-explosion context (CPU-centric limits, data-movement costs, PCIe ceiling) before touching any CXL protocol layer, then through the CXL stack, PCIe foundation, the three CXL protocols (.io / .cache / .mem), the three device types (1 / 2 / 3), memory expansion, memory pooling, coherency fundamentals and CXL coherency flows, fabric architecture and switches, memory devices, performance, security, the CXL 2.0 / 3.0 capability deltas, AI and data-centre case studies, RTL design, verification, debugging, real-industry case studies (AI clusters, memory-expansion cards, hyperscale pools), and the chiplet / composable-infrastructure future.
Tutorials
Learn CXL from beginner to advanced through structured tutorials.
Labs
Practice CXL using progressively challenging hands-on labs.
What CXL is
Compute Express Link is a cache-coherent device-attach protocol that runs over the PCI Express physical layer. A CXL link carries three protocols multiplexed together: CXL.io, which is PCIe transaction traffic used for discovery, configuration and bulk I/O; CXL.cache, which lets a device cache host memory coherently; and CXL.mem, which lets a host address memory that physically lives on the device. The consequence is that a device can expose DRAM the host maps as ordinary memory, and an accelerator can read host memory without a driver-managed copy. CXL is published by the CXL Consortium and has grown across revisions from single-host attach toward switched, multi-host memory pooling and fabric-scale composition.
Why it exists
Processor-attached DRAM stopped scaling with compute along several axes at once — bandwidth per core, capacity per socket, and the energy spent moving bytes between memory domains. Adding cores does not add memory channels, and an accelerator with its own memory pays for every host-device copy in both latency and power. Existing device attach could move data but not share it coherently, so software had to manage copies explicitly. CXL exists to attach memory and accelerators to a host over a link the system already has, with coherence maintained by hardware rather than by driver bookkeeping.
The part engineers get wrong
The useful distinction is between the three protocols, not between CXL and PCIe. CXL.cache and CXL.mem are not two names for the same thing and they do not point the same way: CXL.cache is the device caching the host's memory, while CXL.mem is the host reaching memory attached to the device. Which of the three a device implements is what its type designation means, and it determines the coherence work the design has to do. The second thing to hold early is that CXL does not remove the physics — a link-attached memory access is farther away than a local DRAM access, so CXL widens what memory a system can reach rather than making all of it equally close.
Before you start
- Computer architecture — caches, memory hierarchy and virtual memory
- PCIe fundamentals, since CXL rides the same physical layer and reuses its discovery model
- Helpful: cache-coherence basics such as MESI-style state and snooping
What you will be able to do
- Explain the engineering pressures that made coherent device attach worth standardising
- Distinguish CXL.io, CXL.cache and CXL.mem by direction and by what each is for
- Reason about which device type fits an accelerator or a memory expander
- Explain what memory expansion and memory pooling change about system design
- Discuss where a link-attached memory access costs more than a local one
- Follow a coherent request between host and device at the architectural level
The learning path
- Why CXL existsThe memory wall, data-movement cost, and the limits of non-coherent attach
- CXL overviewWhat the protocol is and how it relates to PCIe
- ArchitectureHost, device and fabric, and the layered stack
- The three protocolsCXL.io, CXL.cache and CXL.mem, and what each carries
- Device typesWhich protocols a device implements, and why that is the classification
- Memory expansion and poolingAttaching memory over a link, and sharing it between hosts
- CoherencyHow host and device agree on the state of a cache line
- Fabric and switchesScaling beyond a single point-to-point link
- Design, verification and debugBuilding and proving a CXL link in RTL
Core concepts
New to CXL? Work through the curriculum in order — each lesson assumes the one before it, and the sequence is what turns the roadmap above into working knowledge.
Already working with it? Use the core-concept links above to jump straight to the topic you need; each one opens the lesson that covers it in most depth.
Where this leads
Standards: CXL Consortium — The body that publishes the Compute Express Link specification