Master the VLSI stack, one domain at a time
Explore the complete VLSI Mentor tutorial library — structured across RTL, verification, protocols, and engineering automation, with every tutorial free to learn.
Every tutorial on this page is free · No paywall
01Core HDL & RTL
Build the language and RTL reasoning foundation — what the code means before how it is written.
Verilog
Digital design fundamentals through synthesizable RTL labs.
SystemVerilog
OOP, randomization, assertions, and functional coverage — IEEE 1800.
VHDL
Strongly-typed HDL for FPGA, aerospace, and defense engineering.
RTL Design Patterns
The design-mastery layer after Verilog — engineer reusable RTL structures.
02Verification
Develop systematic verification and silicon sign-off reasoning, from methodology to gate level.
UVM
Reusable verification methodology built on SystemVerilog.
UVM RAL
Model, drive, and verify a design's registers — the register-verification layer every UVM environment needs.
GLS
Validate the synthesized netlist against real timing — the last functional check before tape-out, taught as a debugging discipline.
DFT
Make a chip testable and prove it good on the tester — scan, ATPG, BIST, and JTAG taught as engineering judgment, not tool commands.
03Protocols & Interfaces
How blocks and chips actually talk — the interconnect fabrics and links a real SoC is built from.
On-chip protocols
AMBA APB
The complete AMBA APB path — protocol, slave RTL, register maps, bridges, verification, debugging, and interviews.
AMBA AHB
The complete AMBA AHB path — bus architecture, wait states, bursts, arbitration, the APB bridge, RTL, verification, and interviews.
AMBA AXI
The complete AMBA AXI path — protocol, RTL, verification, performance, debugging, and interviews.
AMBA CHI
The complete AMBA CHI path — cache coherency first, then nodes, channels, request flows, snoops, directories, RTL, verification, debugging, and interviews.
Wishbone
The complete Wishbone path — open-source on-chip bus from first principles through handshaking, decoding, arbitration, RTL, verification, and RISC-V SoCs.
UART
The engineering path through UART — asynchronous timing first, then framing, baud generation, receiver sampling, RX / TX RTL, FIFOs and flow control, CDC and reset, SoC integration, verification, and waveform debug.
SPI
The complete SPI path — shift-register model, timing and the four CPOL/CPHA modes, framing, bus ownership, flash and QSPI, master and slave RTL, CDC and FPGA timing, verification, and debugging.
I²C
I²C as an engineering system — open-drain electricals and the spec timing table, then transactions, arbitration and clock stretching, then master and slave RTL, FPGA implementation, verification, and waveform debugging.
Off-chip protocols
PCIe
The complete PCI Express path — fabric architecture, enumeration, TLPs, flow control, LTSSM, DMA, RTL, verification, and interviews.
CXL
The complete CXL path — memory wall, coherent attach, three-protocol stack (.io / .cache / .mem), device types, memory pooling, fabrics, RTL, verification, debugging, and interviews.
UCIe
The complete UCIe path — chiplet economics, three-layer UCIe stack, advanced packaging, PCIe / CXL transport, streaming protocol, RTL, verification, debugging, and interviews.
Ethernet
The complete Ethernet path — architecture, the PHY and MAC/PHY boundary, frames, CRC, the MAC datapath, switching, VLANs, timing, PTP, TSN, SoC and DMA, RTL, verification, and debugging.
DDR
The complete DDR path — DRAM fundamentals, DDR architecture, commands, timing parameters, controller, PHY, training, LPDDR, DDR5, HBM, verification, debugging, and interviews.
USB
The complete USB path — host-centric architecture, enumeration, descriptors, transfer types, packets, scheduling, hubs, power, USB 3.x, RTL, verification, debugging, and interviews.
04Low Level Programming Languages
Build the low-level programming foundation used across embedded systems, verification interfaces, firmware, and hardware/software integration.
C Programming
C for semiconductor engineers — processor validation, firmware bring-up, DPI-C verification, memory-subsystem tests, and HW/SW co-verification. The language hardware actually speaks.
C++ Programming
C++ for semiconductor engineers — SystemC, TLM-2.0, virtual platforms, processor/memory/interconnect modeling, reference models, and DPI-C verification.
05Scripting & Automation
Automate builds, regressions, reports, tool flows, and everyday semiconductor engineering workflows.
Linux Bash Shell
Linux + Bash for semiconductor engineers — RTL workspace navigation, simulator launch, filelist automation, regression wrappers, log parsing, EDA env setup, and silicon-bring-up triage.
Tcl
Tcl for semiconductor engineers — synthesis scripting, STA flows, SDC constraints, EDA collections, report parsing, MCMM, PD automation, and EDA-tool customisation.
Python
Python for semiconductor engineers — script-first automation for simulation, regression, log and report parsing, coverage analysis, EDA tool control, and the tests that make a flow script trustworthy.
Makefile
GNU Make for semiconductor engineers — RTL compile, regression drivers, multi-tool flows, synth / STA / wave automation, and the dependency graph every real EDA flow eventually needs.
awk
awk for semiconductor engineers — UVM log parsing, timing/coverage/synthesis/STA report extraction, regression summaries, CSV generation, and metrics pipelines.
sed
sed for semiconductor engineers — mass filelist edits, RTL path migrations, simulator-script updates, SDC rewrites, report cleanup, and safe in-place refactors.
Perl
Perl for semiconductor engineers maintaining legacy EDA infrastructure — report parsing, netlist processing, regression scripts, and the Perl → Python migration path.
