All learning tracks

Long-form tutorials across the modern VLSI stack.

Hand-authored chapters across four hardware-description languages and methodologies. Pick where you want to land — every track is structured so each lesson feeds into the next.

Verilog

Digital design fundamentals, combinational logic, sequential circuits, counters, shift registers, and FSMs — taught through synthesizable RTL examples.

SystemVerilog

The most comprehensive SystemVerilog tutorial — from first principles to advanced verification.

VHDL

VHDL from foundations to advanced — entities, architectures, packages, generics, and rigorous testbenches.

UVM

The complete UVM path — from “what is verification?” through the factory, config_db, phasing, sequences, agents, TLM, scoreboards, coverage, and RAL, to designing, scaling, and debugging industrial UVM environments. Assumes the SystemVerilog track as a prerequisite.

RTL Design Patterns

From describing hardware to engineering it. Reusable, verifiable RTL structures — registers, FSMs, FIFOs, handshakes, arbiters, and clock-domain crossings — with the judgment to choose, parameterize, and verify them.

UVM RAL

UVM Register Abstraction Layer, from your first register model to a multi-bus SoC register environment. Beginner-friendly and working-example driven: read the CSR spec, build the model, wire the adapter and predictor, run the sequences, and — most of all — learn to debug the mirror mismatches and prediction errors that trip up real projects.

GLS

Gate Level Simulation, from your first netlist to a mini-SoC signoff flow. Beginner-to-advanced and debugging-heavy: understand how the gate-level netlist diverges from RTL, back-annotate real delays with SDF, and — most of all — learn to root-cause the X-propagation, reset, and timing-violation failures that only surface once gates and timing enter the picture.

DFT

Design for Testability, from why manufacturing test exists to a full scan + compression + ATPG signoff. Beginner-to-advanced and production-test aware: understand fault models and testability, insert and verify scan, reason about ATPG controllability and observability, add MBIST/LBIST and boundary scan, and — most of all — learn to debug the coverage loss and scan-chain failures that decide whether silicon ships.

Protocols · Free

Industry-grade protocol curricula

Deep, free protocol learning paths — structured the way real semiconductor teams reason about on-chip interconnect.

AMBA AXI

The complete AMBA AXI path — protocol, RTL, verification, performance, debugging, and interviews.

AMBA AHB

The complete AMBA AHB path — bus architecture, wait states, bursts, arbitration, the APB bridge, RTL, verification, and interviews.

AMBA APB

The complete AMBA APB path — protocol, slave RTL, register maps, bridges, verification, debugging, and interviews.

I²C

The complete I²C path — from why two wires and open-drain through arbitration, clock stretching, RTL, verification, debugging, and interviews.

AMBA CHI

The complete AMBA CHI path — cache coherency first, then nodes, channels, request flows, snoops, directories, RTL, verification, debugging, and interviews.

SPI

The complete SPI path — from why synchronous serial through the four modes, full-duplex, QSPI, RTL, verification, debugging, and interviews.

UART

The complete UART path — async first, then framing, baud generation, oversampling, RTL receiver / transmitter, FIFOs, flow control, RTL, verification, debugging, and interviews.

USB

The complete USB path — host-centric architecture, enumeration, descriptors, transfer types, packets, scheduling, hubs, power, USB 3.x, RTL, verification, debugging, and interviews.

PCIe

The complete PCI Express path — fabric architecture, enumeration, TLPs, flow control, LTSSM, DMA, RTL, verification, and interviews.

UCIe

The complete UCIe path — chiplet economics, three-layer UCIe stack, advanced packaging, PCIe / CXL transport, streaming protocol, RTL, verification, debugging, and interviews.

Ethernet

The complete Ethernet path — architecture, MAC/PHY, frames, switching, VLANs, PTP, TSN, RTL, verification, and interviews.

CXL

The complete CXL path — memory wall, coherent attach, three-protocol stack (.io / .cache / .mem), device types, memory pooling, fabrics, RTL, verification, debugging, and interviews.

Wishbone

The complete Wishbone path — open-source on-chip bus from first principles through handshaking, decoding, arbitration, RTL, verification, and RISC-V SoCs.

DDR

The complete DDR path — DRAM fundamentals, DDR architecture, commands, timing parameters, controller, PHY, training, LPDDR, DDR5, HBM, verification, debugging, and interviews.

Programming & Automation · Free

The engineering scripting stack

Linux, Bash, and the build / automation tooling that every semiconductor engineer eventually owns.

Linux Bash Shell

Linux + Bash for semiconductor engineers — RTL workspace navigation, simulator launch, filelist automation, regression wrappers, log parsing, EDA env setup, and silicon-bring-up triage.

Tcl

Tcl for semiconductor engineers — synthesis scripting, STA flows, SDC constraints, EDA collections, report parsing, MCMM, PD automation, and EDA-tool customisation.

Python

Python for semiconductor engineers — simulation/regression automation, log parsing, coverage analysis, report generation, RTL helpers, and EDA flow automation.

Makefile

GNU Make for semiconductor engineers — RTL compile, regression drivers, multi-tool flows, synth / STA / wave automation, and the dependency graph every real EDA flow eventually needs.

awk

awk for semiconductor engineers — UVM log parsing, timing/coverage/synthesis/STA report extraction, regression summaries, CSV generation, and metrics pipelines.

sed

sed for semiconductor engineers — mass filelist edits, RTL path migrations, simulator-script updates, SDC rewrites, report cleanup, and safe in-place refactors.

Perl

Perl for semiconductor engineers maintaining legacy EDA infrastructure — report parsing, netlist processing, regression scripts, and the Perl → Python migration path.

C Programming

C for semiconductor engineers — processor validation, firmware bring-up, DPI-C verification, memory-subsystem tests, and HW/SW co-verification. The language hardware actually speaks.

C++ Programming

C++ for semiconductor engineers — SystemC, TLM-2.0, virtual platforms, processor/memory/interconnect modeling, reference models, and DPI-C verification.

Premium

Spec-grade protocol lessons

Hand-authored protocol deep-dives. Access is admin-approved after payment confirmation.

AMBA-APB Protocol

Understand APB transfers, setup/access phases, PSEL/PENABLE behavior, and low-power peripheral bus design.