Ethernet tutorials, labs & MCQs.
Ethernet for semiconductor engineers — from the shared-medium problem, slot time and packet switching before any frame field, then the end-to-end path from application data through the frame, the MAC, the xMII boundary, the PCS/PMA/PMD stack and onto the wire, and back up the receive path. Frame format and addressing, CRC and the FCS, the MAC transmit and receive datapaths, timing and throughput, six speed generations, the xMII family, auto-negotiation, switching, VLANs, flow control, link aggregation, PTP and TSN, SoC and DMA integration, MAC RTL, verification, debugging, and real switch, NIC and automotive silicon.
Tutorials
Learn Ethernet from beginner to advanced through structured tutorials.
Labs
Practice Ethernet using progressively challenging hands-on labs.
MCQs
No MCQ papers for Ethernet yet.
What Ethernet is
Ethernet is the layer-1 and layer-2 standard that most wired networking is built on, and for a semiconductor engineer it is two blocks and the contract between them. The MAC frames data, applies addresses, appends an error-detecting check value and decides when the medium may be driven. The PHY encodes those bits, serialises them and drives a copper or optical channel, and internally splits again into a coding sublayer, a media-attachment sublayer and the physical medium itself. Between the two sits a media-independent interface — MII and its descendants — which is the boundary a design actually instantiates, and the reason a MAC can be reused unchanged across wildly different physical media. Ethernet is published by the IEEE as 802.3, with VLAN tagging and traffic shaping defined alongside it in 802.1.
Why it exists
Ethernet was created to solve an access problem, not a formatting one: several independent transmitters attached to one physical medium, none able to observe what the others are doing right now. That constraint produced carrier sense, collision detection, a minimum frame size derived from a round-trip propagation bound, and a retry policy — and it explains features of the frame that look arbitrary until the constraint is understood. Switching then removed the shared medium and, with it, most of the original mechanism, while leaving the frame format, the addressing model and the vocabulary intact. What survived is a link layer cheap enough to put in every device and stable enough that the same MAC architecture scales from 10 Mb/s to 800 Gb/s.
The part engineers get wrong
The most useful thing to fix early is the MAC/PHY boundary, because almost every Ethernet design question resolves to which side of it a problem lives on. Framing, addressing, error detection and access control are MAC work and are rate-independent. Coding, serialisation, clock recovery and line drive are PHY work and change completely with every generation. The interface between them is what an RTL engineer connects, and it is where most real integration bugs live — RGMII delay and skew, clock-domain mismatch between a recovered clock and a local one, and management access on a path entirely separate from the data. The second thing worth holding early is that modern switched full-duplex Ethernet has no collision domain: the collision machinery is not how a healthy port works today, and a non-zero collision count on a full-duplex link is a symptom, not normal operation.
Before you start
- Digital design — synchronous logic, state machines and clock domains
- Basic RTL fluency in SystemVerilog or Verilog
- Helpful but not required: any prior exposure to a serial link or an on-chip bus
What you will be able to do
- Explain the shared-medium access problem and why propagation delay makes it a distributed timing problem
- Draw the boundary between MAC and PHY responsibilities and say what crosses it
- Decode an Ethernet frame field by field and say what decision each field drives
- Reason about CRC-32 as generated, as checked, and as built in RTL
- Trace a frame through an SoC from a descriptor ring, through DMA, to the wire and back
- Diagnose the common failure classes: CRC errors, link and negotiation failures, drops and throughput shortfalls
The learning path
- Why Ethernet existsShared media, contention, slot time, and what switching and full duplex changed
- System architectureThe end-to-end path from application data to the wire, and back
- The PHYCopper and fibre, the PCS/PMA/PMD split, block coding, modulation and FEC
- The MAC/PHY boundaryThe xMII contract, clock compensation and PHY management
- Frame and addressingEvery field, grouped by the decision it drives
- CRC and the MAC datapathError detection in three depths, then the transmit and receive paths
- Timing, generations and interfacesSerialisation and throughput, 10M to 800G, and the xMII family
- Switching, VLANs and flow controlLearning, forwarding, segmentation and backpressure
- SoC, RTL, verification and debugDMA and descriptor rings, MAC RTL, assertions and the failure catalogue
Core concepts
New to Ethernet? Work through the curriculum in order — each lesson assumes the one before it, and the sequence is what turns the roadmap above into working knowledge.
Already working with it? Use the core-concept links above to jump straight to the topic you need; each one opens the lesson that covers it in most depth.
Where this leads
Standards: IEEE 802.3 — The working group that publishes the Ethernet standard · IEEE 802.1 — Publishes VLAN tagging, priority and time-sensitive networking alongside 802.3