Simplicity

Chapter 20 compared Wishbone with a bus that is structurally enormous beside it. This module compares it with one that is, by every reasonable measure, just as simple — and the interesting question is what is left to compare when both sides are small.

Both buses are coupled. Both are unpipelined. Both do one transfer at a time. The difference is that APB spends a clock deciding to start.

1. The Word That Means Two Different Things

Start here, because this one trips people who already know both buses.

Both specifications use the word SETUP. B3 uses it 37 times. IHI 0024C uses it 5 times. They are not the same thing and one of them costs a clock.

In B3 the SETUP interval is where the work happens and the transfer finishes on the very next edge. Read the specification's own cycle description: under SETUP, EDGE 1: it says "SLAVE decodes inputs, and responding SLAVE asserts [ACK_I]" — and then CLOCK EDGE 1 completes the transfer.

In APB the SETUP state is where nothing happens yet. It exists so the address and control signals are stable and decoded before PENABLE says "go".

If you carry the Wishbone meaning into an APB conversation, the two-cycle floor looks like an inefficiency somebody could optimise away. It is not, and §4 is why.

2. What The Two Buses Have In Common

Before the difference, the agreements — because they are extensive and they are why this comparison is close.

Six rows of agreement. These are not two philosophies of bus design; they are two spellings of the same one. Chapter 21.3 counts how little the difference costs a peripheral author, and the answer is almost nothing.

3. The Signals You Actually Need

If you are meeting both buses for the first time, this is the table to keep.

B3 states a minimum outright — RULE 3.40:

"As a minimum, the MASTER interface MUST include the following signals: [ACK_I], [CLK_I], [CYC_O], [RST_I], and [STB_O]."

Five signals, and the specification says so. Everything else — [ADR_O], [DAT_O()], [SEL_O()], [ERR_I], [RTY_I], the tags — is optional, and Chapter 19.4 showed how much trouble that optionality causes when two conformant interfaces turn out to be mutually unusable.

IHI 0024C has no equivalent minimal-set rule, because a two-phase protocol has no meaningful one-phase subset. What it has instead is a complete signal list in §2.1, and the shortest useful reading of it is this:

Read the two gaps. APB has an extra row near the top — PENABLE, the second step — and Wishbone has an extra row at the bottom, RTY_I, a "come back later" that APB does not offer.

4. The One Structural Difference

The top row has one box between the master and its answer. The bottom row has two, and the first of them is amber because nothing happens in it that the slave can influence.

Here is the sentence that makes the floor structural rather than incidental:

"The bus only remains in the SETUP state for one clock cycle and always moves to the ACCESS state on the next rising edge of the clock." — IHI 0024C, §4.1

Read "always" as what it is: an unconditional transition. There is no input to that transition. No slave, however fast, is asked. A slave cannot be ready during SETUP because readiness is not the question being posed — PREADY is only meaningful once PENABLE is high.

That is why the specification is able to state the floor as a fact about itself rather than as a property of any particular implementation.

5. The Same Transfer, On Both Buses

SIM A issues workload record 0 — a read of word 0x010 — to both rigs. Same memory contents, same clock, zero wait states on both slaves.

  === SIM A - one transfer each, same workload record ===
    workload entry 0 is a READ of word 0x010. Both rigs hold
    the same memory: mem[k] = 0xAAAA_0000 + k. Both slaves
    have ZERO wait states. Nothing differs but the protocol.

    clk  WISHBONE                    APB
         CYC STB ADR   ACK           PSEL PEN ADDR  PRDY phase
      2   0   0  0x010   0             0    0  0x010   0   idle  
      3   1   1  0x010   1             1    0  0x010   0   SETUP 
      4   0   0  0x020   0             1    1  0x010   1   ACCESS
      5   1   1  0x020   1             1    0  0x020   0   SETUP 
      6   0   0  0x011   0             1    1  0x020   1   ACCESS
      7   1   1  0x011   1             1    0  0x011   0   SETUP 
      8   0   0  0x021   0             1    1  0x011   1   ACCESS

    transfer 0 result   Wishbone 0xaaaa0010   APB 0xaaaa0010
    expected                     0xaaaa0010

    Same value, same memory, same clock domain. The APB
    column spends a clock in SETUP that has no Wishbone
    counterpart, and SIM B counts it.

Follow the phase column. The Wishbone side completes a transfer on clocks 3, 5 and 7. The APB side alternates SETUP, ACCESS, SETUP, ACCESS — and completes on 4, 6 and 8.

Both buses did exactly the same work and returned exactly the same value. One of them used twice as many clocks to do it, and the extra clocks are all in the same place.

6. The Floor, Counted

SIM B runs the whole sixteen-record workload and counts the two phases from the wires — SETUP is PSEL with PENABLE low, ACCESS is both high, so the instrument does not need to be told what the master is thinking.

  === SIM B - the two-phase floor ===
    the whole 16-record workload has now run on both rigs.
    These are the APB phase counters, taken from the wires:
    SETUP is PSEL with PENABLE low, ACCESS is both high.

      transfers completed            16
      clocks in SETUP                16
      clocks in ACCESS               16
      of which were waits            0
      transfers with NO setup phase  0

      fewest clocks any transfer took   2
      most clocks any transfer took     2

      NO TRANSFER COST FEWER THAN TWO CLOCKS, and with
      zero wait states none cost more. The specification
      says this of itself:
        "The APB protocol is not pipelined... Every
         transfer takes at least two cycles."
                              (ARM IHI 0024C, s1.1)
      and the state machine says why:
        "The bus only remains in the SETUP state for one
         clock cycle and always moves to the ACCESS state
         on the next rising edge of the clock."
                              (ARM IHI 0024C, s4.1)

Sixteen transfers, sixteen SETUP clocks: exactly one each. And the minimum and maximum are both 2, because with zero wait states there is nothing to extend.

7. What Wishbone Does With That Clock

  === SIM C - the same work on Wishbone ===
    identical records, identical memory, zero wait states.

      measure                        Wishbone   APB
        transfers completed              16         16
        clocks a transfer was running    16         32
        clocks per transfer             1.00       2.00

      The Wishbone RAM answers COMBINATIONALLY, which B3
      permits in as many words:
        "If the SLAVE guarantees it can keep pace with all
         MASTER interfaces and if the [ERR_I] and [RTY_I]
         signals are not used, then the SLAVE's [ACK_O]
         signal MAY be tied to the logical AND of the
         SLAVE's [STB_I] and [CYC_I] inputs."
                              (B3, PERMISSION 3.10)
      So one clock is not a trick and not an optimisation.
      It is a permitted slave design, and APB has no
      equivalent permission to grant.

One clock per transfer, and it is not a trick.

The Wishbone RAM used here is Chapter 16.4's, reused byte-for-byte unchanged, and it answers combinationally — [ACK_O] tied to the AND of [STB_I] and [CYC_I], exactly as PERMISSION 3.10 describes.

APB has no equivalent permission to grant, because the thing that would need permission — a slave answering during SETUP — is not expressible. PREADY is not sampled until PENABLE is high.

8. Two Ways To Leave ACCESS, And One Costs A Clock

SIM D measures a choice the specification offers explicitly, because the intuition about it is usually wrong.

  === SIM D - back-to-back, and the PSEL intuition ===
    Section 4.1 names TWO conformant ways to leave ACCESS:
      "the bus returns to the IDLE state if no more
       transfers are required. Alternatively, the bus moves
       directly to the SETUP state if another transfer
       follows."
    Both are legal. One costs a clock per transfer:

      rig                    xfers  SETUP  ACCESS  wall clocks
      ACCESS -> SETUP direct    16     16     16       31
      ACCESS -> IDLE -> SETUP   16     16     16       46

      EXACTLY ONE SETUP CLOCK PER TRANSFER IN BOTH. The
      common intuition that holding PSEL saves the setup
      cycle is wrong: SETUP is defined by PENABLE being
      LOW, not by PSEL rising. Holding PSEL removes the
      IDLE clock and nothing else.

      The IDLE path cost 15 extra clocks over 16
      transfers - one each. Both rigs are conformant and
      one is 50% slower, which is a reminder that a
      protocol comparison measures an IMPLEMENTATION of a
      protocol unless you are careful about which one.

      Neither bus pipelines. Wishbone's RULE 3.35 makes the
      termination the answer to the one request on the
      wires; APB says outright that it "is not pipelined".

Holding PSEL does not save the SETUP clock. SETUP is defined by PENABLE being low, not by PSEL rising — so the bus passes through it either way. What holding PSEL saves is the IDLE clock between transfers, and that is worth exactly one clock per transfer.

Both paths are conformant and one is 50% slower. That is worth sitting with: a protocol comparison measures an implementation of a protocol unless you are careful about which implementation. The first draft of this module's APB master returned to IDLE between every transfer, and it made APB look a third worse than it is.

9. So Which One Is "Simpler"?

Neither, in any way that survives being counted. Here is the count, over this module's own RTL — the same job written twice, by the same author, in the same style, in the same session.

    pair        measure          Wishbone   APB     ratio
    memory      handshake phases     1         2    2.00x
    memory      port signals        27        29    1.07x
    memory      FSM states           0         0    -
    memory      code lines          53        64    1.21x

    peripheral  handshake phases     1         2    2.00x
    peripheral  port signals        27        27    1.00x
    peripheral  FSM states           0         0    -
    peripheral  code lines          53        54    1.02x

10. Where This Module Goes