Wishbone · Module 20
Performance Comparison
One identical workload, two protocols, two slave latencies — and the sign of the difference reverses between the tables. Plus the complete list of performance claims this module refuses to make.
This chapter begins with what it will not claim, because the refusals are load-bearing.
Some performance questions can be counted in a simulator. Others cannot be answered without silicon. Mixing the two produces a number that is citable and wrong.
1. The Refusal List
No synthesis tool was run on any RTL in this module. No place-and-route, no timing analysis, no library. The following therefore appear nowhere in Module 20, and anyone who tells you one of them without showing you a report has not measured it either:
| refused | why it cannot be claimed here |
|---|---|
| fmax for either protocol | a function of the netlist, the library, the constraints and the tool — none of which exist in this module |
| gate count / LUT count / area | a port is not a wire; a line of RTL is not a flip-flop |
| power | requires switching activity on a real netlist |
| MB/s, GB/s, any absolute bandwidth | requires a clock period, which requires timing closure |
| "AXI is faster than Wishbone" | see §3 and §4 — the sign of the difference reverses on identical work |
| "Wishbone is lighter" | plausible, widely repeated, and not measured here |
What can be counted, and is:
| measured | where |
|---|---|
| clocks to complete a fixed workload | §3, §4 |
| maximum outstanding transactions the protocol permits | §2 |
| clocks a master had work and nothing in flight | §5 |
| addresses accepted while an earlier answer was outstanding | §2 |
| distinct addresses sent for an N-word transfer | §5 |
| what a reordering costs | §6 |
2. One Workload, Read By Both Masters
The comparison is worthless unless both protocols do exactly the same work. In this module that is guaranteed structurally rather than by care: there is one wl_workload instance per testbench and both masters index into it.
// ─────────────────────────────────────────────────────────────────────────
// wl_workload — ONE workload, read by both protocol rigs.
//
// This module exists to make a comparison honest. The methodological
// failure that would ruin Module 20 is comparing a Wishbone system to an
// AXI system doing different work, and the cheapest way to make that
// impossible is to have exactly one description of the work and let both
// masters read it.
//
// There is ONE INSTANCE of this module in every comparison testbench. The
// Wishbone master and the AXI master each have their own index port into
// it. They cannot diverge, because there is nothing to diverge from.Sixteen records — nine reads, seven writes, three of them sub-word so the byte-strobe path is exercised, and addresses that revisit words already written so a scoreboard can catch a lost or misdirected write.
SIM D measures how much of the work each protocol could have in flight at once.
=== SIM D - outstanding depth, same workload ===
the workload is 16 records: 9 reads, 7 writes, three of
them sub-word. Every rig below ran exactly those.
rig deepest out AW+AR accepted
while unanswered
Wishbone (any latency) 1 0
AXI fast MAXOUT 4 2 1
AXI slow MAXOUT 4 4 14
AXI slow MAXOUT 1 1 0
clocks with a read AND a write both in flight
AXI fast 0 AXI slow 35 AXI slow/MAXOUT1 0
-> Wishbone's value here is structurally zero. One
[ADR_O], one [WE_O]: the access in flight is a read
or it is a write, never both.Wishbone's row is not a tuning result. It is 1 and 0 and 0 at every latency, for the reason Chapter 20.1 established: one [ADR_O], one [WE_O], RULE 3.60 qualifying both with [STB_O].
The last line is the one to keep. Thirty-five clocks on which the AXI rig had a read and a write simultaneously in the air. A Wishbone master's value for that is structurally zero — the access in flight is a read or it is a write.
3. The First Table: Fast Slaves
=== SIM E - FAST slaves, zero wait states ===
clocks from start to the sixteenth answer.
Wishbone 34 clocks
AXI-Lite 36 clocks
difference 2 clocks in Wishbone's favour
READ THIS ONE CAREFULLY BEFORE DRAWING A CONCLUSION.
The Wishbone RAM answers COMBINATIONALLY. B3 permits
exactly that:
"If the SLAVE guarantees it can keep pace with all
MASTER interfaces and if the [ERR_I] and [RTY_I]
signals are not used, then the SLAVE's [ACK_O]
signal MAY be tied to the logical AND of the
SLAVE's [STB_I] and [CYC_I] inputs."
(B3, PERMISSION 3.10)
The AXI-Lite slave registers its response, which is
the ordinary way to build one. THAT ONE-CLOCK
DIFFERENCE IS A SLAVE IMPLEMENTATION CHOICE, NOT A
PROTOCOL PROPERTY, and it is stated rather than
quietly banked as a win for Wishbone.
What IS a protocol property: with no wait states there
is almost nothing for extra channels to overlap. The
decoupling had 1 opportunities and the coupled
protocol lost nothing by not having it.Wishbone finished first. Thirty-four clocks against thirty-six.
And the honest explanation is printed with the result rather than left for the reader to discover. Two of those clocks are a slave implementation difference, not a protocol one: the Wishbone RAM answers combinationally, which PERMISSION 3.10 expressly allows, while the AXI-Lite slave registers its response the way an AXI-Lite slave normally does.
The protocol part of the result is the other observation: with no wait states there is nothing to overlap. The decoupling had one opportunity in sixteen records and the coupled protocol lost nothing by not having it.
4. The Second Table: Slow Slaves
Identical workload. Identical memory. Identical master. Three wait states on both sides. Nothing else changed.
=== SIM F - SLOW slaves, three wait states ===
identical workload, identical memory, both slaves now
take three extra clocks. Nothing else changed.
Wishbone 82 clocks
AXI-Lite MAXOUT 1 114 clocks
AXI-Lite MAXOUT 4 49 clocks
AXI MAXOUT 4 against AXI MAXOUT 1 65 clocks saved
AXI MAXOUT 4 against Wishbone 33 clocks FASTER
AXI MAXOUT 1 against Wishbone 32 clocks SLOWER
-> the AXI rig that does not USE its channels is the
slowest thing in the table. Five channels cost
handshakes whether or not anything overlaps.
THE COMPARISON THAT MATTERS is the middle row against
the bottom row: same protocol, same slave, same work,
one parameter. Everything separating them is the
decoupling being used.
E vs F - the difference between the two tables:
fast Wishbone 34, AXI/4 36 gap 2
slow Wishbone 82, AXI/4 49 gap 33
THE SIGN OF THE DIFFERENCE REVERSED BETWEEN THE TWO
TABLES. Wishbone was ahead with fast slaves and behind
with slow ones, on identical work. A single benchmark
number for "which bus is faster" would have been
true, citable, and worthless.The middle row is the most useful line in the table and it is the one nobody expects. AXI-Lite restricted to one outstanding transaction took 114 clocks — thirty-two clocks slower than Wishbone on the same slaves.
Five channels cost handshakes whether or not anything overlaps. An AXI system that does not use its decoupling has paid for it and received nothing. That is not a criticism of AXI; it is a statement about what the extra structure is for, and it is the strongest argument in this module against reaching for AXI reflexively.
5. Bursts Against Block Cycles
The comparison that would have been rigged is one AXI burst against N separate Wishbone SINGLE cycles. Wishbone has a block cycle and RULE 3.25 covers it — "MASTER interfaces MUST assert [CYC_O] for the duration of SINGLE READ / WRITE, BLOCK and RMW cycles" — so one [CYC_O] spans the block exactly as one ARVALID spans the burst. That is the honest pairing, and it is what SIM G runs.
measure Wishbone AXI4
words delivered 8 8
distinct addresses sent 8 1
clocks an address was driven 32 1
RLAST / final termination 1 1
data signature 0xadf3d1d7 0xadf3d1d7
Same 8 words, same order, identical signature.
THE DIFFERENCE IS NOT THE CLOCK COUNT. It is 8
distinct addresses against 1. B3 RULE 3.60 qualifies
[ADR_O] with [STB_O] on EVERY transfer, so a block
cycle re-presents a full address per word - and holds
it for all 4 clocks of every wait state, which is the
32-clock figure above. An AXI burst sends ONE address
and a length:
"AXI4 extends burst length support for the INCR
burst type to 1-256 transfers." (A3.4.1)
What that buys is not measured here as area or wires,Identical data, identical order, identical signature. The difference is not the clock count.
It is eight distinct addresses against one. And the 32-clock figure is worth a second look: because RULE 3.60 qualifies [ADR_O] with [STB_O], the address is not merely re-sent per word — it is held on the wires for every clock of every wait state. An AXI burst sends one address and a length.
What that buys is not measured here as area or wires, for the reasons in §1.
Chapter 20.3 refusal list.
THE COST OF A BURST THAT IS THE WRONG SIZE
A master that asked for 8 and needs 4 cannot simply
stop. The specification is explicit for writes -
"the master can disable further writing by
deasserting all the write strobes. In this case, the
master must complete the remaining transfers in the
burst." - and for reads: "the master can discard
read data, but it must complete all transfers in the
burst."
So the 4 unwanted beats are still delivered and still
occupy the read data channel. A Wishbone block cycle
negates [CYC_O] and stops. Neither is free: one wastes
beats, the other re-sends addresses.A burst that is the wrong size cannot be abandoned. The specification is explicit for writes and for reads, and a Wishbone block cycle simply negates [CYC_O] and stops. Neither is free: one wastes beats, the other re-sends addresses.
6. The Ordering Cost — The Half That Usually Gets Left Out
SIM H issues two read bursts with different IDs, back to back, without waiting.
=== SIM H - two outstanding reads, and their order ===
two bursts of 8 words, IDs 0 and 1, issued back to
back without waiting. Two slaves, identical except that
one returns the second burst first.
rig bursts beats RLASTs RID order (hex)
in order 2 16 2 0x55550000
reordered 2 16 2 0x00005555
the RID order word packs each returned beat's RID two
bits at a time, oldest in the LOW bits. ID 0 is 2'b00
and ID 1 is 2'b01, so eight beats of ID 0 followed by
eight of ID 1 reads 0x55550000 - the zeros are the
first burst - and the reverse reads 0x00005555. THE ORDER DIFFERED AND BOTH ARE LEGAL. Two reads
with different IDs have no ordering guarantee
between them - the specification lists exactly that
case - so a master that cared has to do something
about it. IHI 0022H A6 says what:
"If a master requires ordering between
transactions that have no ordering guarantee, the
master must wait to receive a response to the
first transaction before issuing the second
transaction."
READ THAT AS A COST. The remedy for needing order
is to stop having two transactions outstanding -
which is Wishbone's permanent, unavoidable state.
AXI does not remove the coupling; it makes the
coupling OPTIONAL, and hands you the bookkeeping.
data signatures in order 0xf3e2df99 reordered 0xf3e52061
=== errors: 0 ===7. What The Decoupling Changed On The Full Workload
SIM J runs the whole comparison and checks whether the four rigs agreed.
2. DID EVERY RIG GET THE SAME ANSWERS?
order-sensitive signature over (index, data, error)
WB fast 0x98b97cbd
AXI fast 0x98b97cbd
WB slow 0x98b97cbd
AXI slow MAXOUT 1 0x98b97cbd
AXI slow MAXOUT 4 0x67468348 <-- DIFFERENT
The four ORDERED rigs agree exactly. The fifth does
not, and it is the most important number in this
module.Four signatures match. The fifth does not.
WHAT DIFFERED, PRECISELY: THE ORDER, NOT THE DATA.
Section 7 prints all sixteen values side by side
and every one of them matches. The signature is
order-sensitive, so what separates 0x67468348 from
0x98b97cbd is the SEQUENCE the answers arrived in.
answers that did not follow their predecessor
WB fast 0 AXI fast 0 WB slow 0
AXI slow MAXOUT 1 0 AXI slow MAXOUT 4 3
That is the protocol behaving exactly as written.
Ordering is NOT guaranteed between:
Transactions from different masters
Read and write transactionsEvery value was correct. Section 7 of the audit prints all sixteen side by side and they match; what differed was the sequence the answers arrived in. Three answers in the deep rig did not follow their predecessor, because write responses and read data return on separate channels and A6.1 lists "Read and write transactions" among the pairs with no ordering guarantee.
Nothing was wrong, nothing was lost, and nothing was violated. Whether that reordering matters depends entirely on what the software does with the answers — which is precisely why the specification refuses to decide it for you.
"If a master requires ordering between
transactions that have no ordering guarantee,
the master must wait to receive a response to
the first transaction before issuing the second
transaction." (IHI 0022H, A6)
THE MAXOUT 1 ROW IS THAT INSTRUCTION OBEYED, and
its signature matches Wishbone's exactly. The
remedy for needing order is to stop having two
transactions outstanding - which is the permanent,
unavoidable state of a Wishbone master.
AXI DOES NOT REMOVE THE COUPLING. It makes the
coupling OPTIONAL and hands you the bookkeeping.
Chapter 20.5 records what happened when this
module's own AXI master got that bookkeeping wrong.8. The Summary Worth Keeping
| slaves | Wishbone | AXI, 1 outstanding | AXI, 4 outstanding |
|---|---|---|---|
| fast (0 waits) | 34 | — | 36 |
| slow (3 waits) | 82 | 114 | 49 |
Three readings of the same system, all true:
- With fast slaves, the coupled protocol is marginally ahead and the channels are idle overhead.
- With slow slaves and the decoupling used, AXI finishes in 60% of Wishbone's time.
- With slow slaves and the decoupling unused, AXI is 39% slower than Wishbone.
The protocol did not decide any of those. The slave latency and the master's outstanding depth did.
Continue learning
Related tutorials
- Related topic
Mastering Memory over AXI
The same misalignment costs 1.40 percentage points of bus efficiency and 37% of the transaction budget, and only one of those two numbers is the one that binds.
- Related topic
Performance Considerations
A block cycle saves exactly N-1 clocks over N single cycles, independent of slave latency — and that saving vanishes if the master throttles. Measured, including the latency it costs every other master.
- Related topic
Throughput Improvements
The saving from retaining CYC is a constant; slave latency is a multiplier. Measured: 1.6x decaying to 1.18x with nothing in either design changing.
- Related topic
Complexity Comparison
Wishbone couples address, data and response into one phase; AXI separates them into five independent channels. Both specifications say so normatively, and every other difference in the module is a consequence.
Standards & specifications
- Governing standard
- Wishbone SoC Interconnection Architecture (OpenCores)(opens OpenCores in a new tab)
Defines the Wishbone signal set, the bus cycles built from it and the interface rules a portable IP core must follow. It deliberately leaves interconnect topology, address map and arbitration policy to the integrator, so those are system decisions rather than requirements of the specification.
This page also covers RTL structure, verification approach and debugging technique. Those are engineering practice built on the standard, not requirements the standard itself imposes.
Where this fits
Part of the Wishbone curriculum.