Use Cases

"Which bus should I use" is partly a question about silicon and partly a question about intent. The first part can be counted. The second is settled by reading what each specification says it is for — which is evidence, not opinion, provided you quote it rather than paraphrase it.

Both documents state their purpose in their first chapter. They are not competing for the same job.

1. What Each Specification Says It Is For

Neither of these is inference. Both are first-chapter statements of purpose.

Wishbone B3, opening sentence and glossary:

"The WISHBONE System-on-Chip (SoC) Interconnection Architecture for Portable IP Cores is a flexible design methodology for use with semiconductor IP cores. Its purpose is to foster design reuse by alleviating System-on-Chip integration problems. This is accomplished by creating a common interface between IP cores."

"A flexible System-on-Chip (SoC) design methodology... Its purpose is to foster design reuse, portability and reliability of SoC designs. WISHBONE is a public domain standard."

And among its stated objectives:

"to create a portable interface that is independent of the underlying semiconductor technology. For example, WISHBONE interconnections can be made that support both FPGA and ASIC target devices."

AMBA APB, IHI 0024C §1.1:

"The APB protocol is not pipelined, use it to connect to low-bandwidth peripherals that do not require the high performance of the AXI protocol... The APB can interface with: Advanced High-performance Bus (AHB), Advanced High-performance Bus Lite (AHB-Lite), Advanced Extensible Interface (AXI), Advanced Extensible Interface Lite (AXI4-Lite). You can use it to access the programmable control registers of peripheral devices."

So one document describes a general interconnect and the other describes a destination. That is not a ranking. A bus designed to be the end of a hierarchy is not a worse bus; it is a bus with fewer obligations, and §3 counts how few.

2. What Was Counted

Three pairs of modules, each pair doing the same job, written by the same author in the same style in the same session, differing only in protocol.

  === MECHANICAL COMPLEXITY COUNT ===
    over this module's own RTL. Same job, same author, same
    session, two protocols. No synthesis was run and no number
    below is an area, gate-count or frequency figure.

    pair        measure          Wishbone   APB     ratio
    memory      handshake phases     1         2    2.00x
    memory      port signals        27        29    1.07x
    memory      FSM states           0         0    -
    memory      code lines          53        64    1.21x

    peripheral  handshake phases     1         2    2.00x
    peripheral  port signals        27        27    1.00x
    peripheral  FSM states           0         0    -
    peripheral  code lines          53        54    1.02x

    master      handshake phases     1         2    2.00x
    master      port signals        51        52    1.02x
    master      FSM states           0         3    -
    master      code lines          77        98    1.27x

3. What APB Actually Costs A Peripheral Author

The peripheral row is the fairest comparison in that table and the most surprising: 27 port signals against 27, and 53 code lines against 54.

wb_tiny_gpio and apb_tiny_gpio are four registers with three access policies — read/write, read-only with a refused write, and write-one-to-clear. The register bank is line-for-line identical between them. Here is what actually changed:

// the flag logic are line-for-line the same. What changed is the part that
// decides WHEN a register is allowed to act, and it grew from
//
//     xfer = cyc_i && stb_i
//
// to a two-phase condition, because on APB a peripheral must not act in
// SETUP:
//
//     in_access = psel_i && penable_i
//     ready     = in_access                (this slave inserts no waits)
//
// That is the honest measure of what APB costs a peripheral author: one
// extra term and the knowledge of why it is there. It is not nothing, and
// it is not much.

One extra term, and the knowledge of why it is there.

Four rows and three of them are a rename. The one that is not a rename is the first, and it is one &&.

4. What The Master Pays Instead

The peripheral pays one &&. The master pays a state machine, and this is where APB's structure actually lands.

        // one clock, unconditionally. Nothing is sampled here.
        S_SETUP: begin
          nsu_q <= nsu_q + 16'd1;
          st_q  <= S_ACCESS;
        end
        S_ACCESS: begin
          nac_q <= nac_q + 16'd1;
          if (pready_i) begin
            ndn_q <= ndn_q + 16'd1;
            idx_q <= idx_q + 5'd1;
            if ((idx_q + 5'd1) >= count_i[4:0]) begin
              run_q <= 1'b0;
              st_q  <= S_IDLE;
            end else if (HOLD_PSEL) begin
              // "the bus moves directly to the SETUP state if another
              //  transfer follows"  - no IDLE clock, PSEL stays asserted
              st_q  <= S_SETUP;
              nis_q <= nis_q + 16'd1;
            end else begin
              // "the bus returns to the IDLE state" - also conformant,
              // and one clock per transfer more expensive
              st_q  <= S_IDLE;
            end
          end
        end

Three states, and the transition out of SETUP takes no argument. There is no input to it, no condition, nothing to get wrong — which is also why Chapter 21.4 §6 finds it checkable in a way Wishbone's equivalent is not.

The Wishbone master has no state machine at all. It has a single busy flag: a request is open or it is not, and the termination closes it. The complexity count records this as 0 FSM states against 3.

So the honest distribution of APB's cost is:

A system has many peripherals and one bridge. APB put its cost where there is one of them. That is the design working, and it is only visible if you count the two sides separately.

5. What Each Specification Asks A Newcomer To Read

Counted from the two documents this session:

APB is the shorter document by a wide margin, and its three-state machine is the most compact complete description of a bus in this entire curriculum. That is a real advantage and it is not hedged here.

Wishbone's advantage is RULE 3.40 — a stated five-signal minimum, which tells a beginner exactly where to stop. IHI 0024C has no counterpart, because a two-phase protocol has no meaningful one-phase subset.

6. The Judgement, And Its Assumptions

THIS IS A DESIGN JUDGEMENT, NOT A MEASUREMENT. Stated plainly so it can be disagreed with:

Choose APB when the thing you are attaching is a register block behind a bridge and the extra clock does not matter. Choose Wishbone when the bus is the system's interconnect rather than its last hop, or when the slave can answer immediately and you want that clock back.

It rests on these assumptions, and rejecting one weakens it:

1. The extra clock is genuinely affordable in the APB case. For configuration registers written at boot, it is. For a peripheral in a tight polling loop, 21.2 §3 says it doubles your access time.
2. There is a bridge. APB's own §1.1 assumes one and its signal table names it. If there is no upstream bus, APB is being used outside its stated purpose — which is allowed, and is a decision worth making on purpose.
3. The peripheral count exceeds the master count, so the per-peripheral cost matters more than the per-master cost. §3 and §4 say that trade is APB's whole shape.
4. Ecosystem fit dominates. If the rest of the SoC is AMBA, APB is what bridges from AHB or AXI without a translation layer — and §1 quotes IHI 0024C naming all four.
5. "Public domain" is a real property, not a slogan. B3's glossary says it in as many words, and it is why this curriculum could quote B3 in full and could only quote 21 pages of APB under its Non-Confidential marking.

What would change my mind: evidence that the SETUP clock costs more than one clock in real interconnects with registered bridges; or a peripheral-side count on a larger, more realistic peripheral where the two-phase condition propagates further than the one && measured here. Neither has been measured, by me or by anyone cited.

7. What Each Bus Does Not Teach Or Give You

Being honest about this is the price of §6.

And neither gives you what Chapter 20 measured: outstanding transactions, response reordering, transaction IDs, or independent channels. On that axis Wishbone and APB are the same bus with different spelling, and AXI is the one that is different.

8. What Neither Bus Settles

The peripheral's own behaviour, which is where Chapter 19.5's finding arrives unchanged. SIM H put the identical refused write on both buses:

      write IN (read-only)       wr  0x00000000  0x00000000            match

      error flagged   Wishbone ERR_O 1   APB PSLVERR 1
      -> BOTH REFUSED IT, and neither specification told
         them to. B3 PERMISSION 3.20 says outright: "This
         specification does not dictate what the MASTER
         does in response to [ERR_I]." IHI 0024C s1.2.2
         says only that PSLVERR is "an error signal to
         indicate the failure of a transfer". WHAT COUNTS
         AS A FAILURE IS THE PERIPHERAL'S OWN POLICY on
         both buses - Chapter 19.5's finding, arriving
         here unchanged.

    THE STICKY FLAGS - hardware sets, the bus clears
      write DIR = 0x00           wr  0x00000000  0x00000000            match

Both refused it, and neither specification told them to.

B3's PERMISSION 3.20 says outright: "This specification does not dictate what the MASTER does in response to [ERR_I]." IHI 0024C §1.2.2 says only that PSLVERR is "an error signal to indicate the failure of a transfer".

What counts as a failure is the peripheral's own policy on both buses. Choosing a bus does not choose that, does not choose your register map, and does not choose whether a write-one-to-clear bit is the right design. Those are the decisions that actually determine whether a peripheral is good, and both specifications decline to make any of them.

9. The Defensible Summary