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VLSI Mentor

Wishbone · Module 31

"Wishbone Cannot Scale"

Eleven dimensions hide in one word. Measured: 49 cycles against 41 with independent targets, and 49 against 49 when both masters want the same slave.

"Scale" is the most overloaded word in interconnect discussion. Before it can be true or false, somebody has to say which dimension.

1. Eleven Dimensions, One Word

dimensiondoes Classic constrain it?
number of mastersno — arbitration is yours
number of slavesno — decoding is yours
address space sizeno — ADR_O is as wide as you make it
clock frequencyindirectly — a combinational termination path is real
aggregate throughputpartly — and mostly through topology
outstanding transactionsYES — one, by construction
physical fanoutno — an implementation concern
arbitration complexityno — not specified at all
routing complexityno — not specified at all
verification complexitygrows with topology, not with the protocol
software-visible map sizeno

Two rows are genuine protocol limits. The rest are properties of what you built around it. A claim about row six does not establish anything about rows one, two or five — and those are the rows people usually mean.

2. Protocol Is Not Topology

This distinction carries the chapter.

The Wishbone specification describes an interface between two endpoints. It says nothing about how many endpoints exist or how requests reach them. Module 18 built both topologies; Module 29 found both in one framework's source, nine lines apart — the same arbiter and decoder blocks, composed in the opposite order.

The same interface used in two topologies. On the left, two masters feed an arbiter whose single output is one shared interface, which is then decoded to two slaves. Every transfer in the system passes through that single shared interface, so two transfers cannot be in flight at once regardless of where they are going. On the right, each master has its own decoder feeding a row of access interfaces, and each slave has its own arbiter over a column of them, so no single shared interface exists. Both diagrams use the identical Wishbone interface at every port; only the composition differs. A note records that the protocol constrains neither arrangement.M0 M1sharedone arbiterONE sharedinterfacethe serialisationpointone decoderS0 S1M0 M1crossbardecoder permasterarbiter perslaveno shared interfaceS0 S1same interfaceat every portthe protocolconstrains neitherarrangement12

So the claim usually means:

"One particular shared-bus topology does not scale for my workload."

Which is frequently true, and is a statement about a topology and a workload.

3. Measured

Two masters, eight operations each, one-wait slaves. One dimension — aggregate transfers per clock — across two topologies and three workloads. The topologies are VLSI Mentor reconstructions of the LiteX classes inspected in Module 29; no number here is a measurement of LiteX.

Azvya Education Pvt. Ltd.VLSI Mentor
Snippet
  workload / topology              M0 ops   M1 ops    total   cycles used  concurrent clk
  SIM B shared, gaps of 6             8         8       16           91             0
  SIM C shared, indep targets         8         8       16           49             0
  SIM D crossbar, indep targets       8         8       16           41             8
  SIM E shared, SAME target           8         8       16           49             0
  SIM E crossbar, SAME target         8         8       16           49             0
Azvya Education Pvt. Ltd.VLSI Mentor
Snippet
  per-master clocks presented (the cost of waiting)
    SIM C shared    M0 23   M1 25
    SIM D crossbar  M0 16   M1 17
    SIM E shared    M0 23   M1 25
    SIM E crossbar  M0 23   M1 25

Three readings, in order of how much they matter.

With independent targets the topology is worth something. 49 cycles against 41, and 8 clocks on which two transfers were genuinely in flight against 0. Per-master presented clocks fall from 23/25 to 16/17 — the masters spend less time waiting.

With one target the topology is worth exactly nothing. 49 against 49. Zero concurrent clocks in both. Per-master presented clocks identical. The crossbar still has two arbiters and two decoders; the limit simply moved to the slave, and no routing arrangement makes a one-wait slave accept two transfers at once.

And the third row is the one that traps people. SIM B — the same shared bus with masters that pause between operations — took 91 cycles for the same 16 transfers. Slower in wall-clock terms than either continuous case, and the bus was never the reason. If you benchmark this configuration and conclude the shared bus is a bottleneck, you have measured your stimulus.

4. What This Measurement Does And Does Not Support

SUPPORTED. Under two masters issuing continuously to independent one-wait targets, this reconstructed crossbar completed 16 transfers in 41 cycles where this reconstructed shared interconnect took 49, and had 8 clocks with both slaves selected against 0. Under the same traffic aimed at one target, both took 49 cycles with 0 concurrent clocks.

NOT SUPPORTED. That crossbars are faster. That shared buses are unsuitable. That Wishbone scales, or does not. Anything about frequency, area, power, more than two masters, or any real workload. Anything about LiteX, whose source these models reconstruct but do not measure.

Every performance sentence in this curriculum carries that second paragraph. Without it, the first one becomes the slogan this chapter exists to dismantle.

5. The Real Limits, Stated Plainly

A chapter that only defended the protocol would be useless. Four limitations that are genuine, and only the first two are about Wishbone:

One outstanding transfer, in Classic. A phase is a request held until its termination; there is nowhere for a second to be. Module 29 measured 1 against 4 outstanding on the same eight operations across a Classic and a pipelined model, 41 cycles against 20. This is a protocol property and no topology repairs it. A pipelined profile is a different contract, not a configuration option.

No native transaction identity. Nothing in Classic distinguishes one outstanding request from another, because there is only ever one. Out-of-order completion has no vocabulary here.

Arbitration and routing cost grows with the topology, not the protocol. A crossbar is N decoders and M arbiters; that is multiplexer depth and area somebody pays. The protocol did not ask for it and does not forbid it.

Verification burden grows fastest of all. Chapter 30.4 measured 133 misdelivered responses with zero specification violations — an invariant that only exists once you have more than one master, and that nothing in the protocol will check for you.

Scalability is a vector, not a boolean. Two of these four limits are real Wishbone constraints; two are the price of the system you built.

6. The Design Consequence

Believing the slogan produces two symmetric mistakes.

Replacing the protocol when the topology was the problem. If your bottleneck is one shared interface serialising traffic to independent targets, a crossbar built from the same blocks addresses it — 49 to 41 above. Swapping protocols instead is a far larger change that may not touch the actual constraint.

Replacing the topology when the slave was the problem. SIM E is the counterexample: same traffic, one target, 49 against 49. A crossbar bought nothing and cost two arbiters and two decoders.

Both are the same error — acting before naming the dimension.

7. The Replacement Statement

Instead of"Wishbone cannot scale."
Say"Classic is limited to one outstanding transfer per master and has no transaction identity — those are protocol limits no topology removes. Everything else usually attributed to scale is topology: under continuous traffic to independent targets our reconstructed crossbar completed the same 16 transfers in 41 cycles against the shared interconnect's 49, and when both masters targeted one slave both took 49. Name the dimension and measure it."

8. What To Carry Forward

  • Name the dimension. Eleven live in the word, and only two are protocol limits.
  • Protocol is not topology. The same interface appears in both arrangements, nine lines apart in one real framework.
  • Every performance claim needs a workload, and a NOT-SUPPORTED paragraph.
  • When the target is the limit, routing buys nothing — 49 against 49.
  • A benchmark whose masters idle measures the idling. 91 cycles for the same 16 transfers.
  • State the real limits. One outstanding transfer is a genuine constraint and saying so is what makes the rest credible.

Chapter 31.3 turns to a word that is not a technical property at all.

Continue learning

Standards & specifications

Governing standard
Wishbone SoC Interconnection Architecture (OpenCores)(opens OpenCores in a new tab)

Defines the Wishbone signal set, the bus cycles built from it and the interface rules a portable IP core must follow. It deliberately leaves interconnect topology, address map and arbitration policy to the integrator, so those are system decisions rather than requirements of the specification.

This page also covers RTL structure, verification approach and debugging technique. Those are engineering practice built on the standard, not requirements the standard itself imposes.

Where this fits

Part of the Wishbone curriculum.