"ACK Must Assert Immediately"

This is the one misconception in the module that a specification can settle directly — which makes it the one worth being most precise about.

The correction in a sentence: ACK_O is a transfer termination, not a same-cycle response requirement. But stopping there teaches nothing, because the belief has a real source.

1. Where The Belief Comes From

Three reasonable observations, compressed:

Every diagram people first meet has a one-clock transfer. The canonical single read and single write figures show a request and an acknowledgement adjacent. That is the simplest legal case, presented first, and nothing in the figure announces that it is one of many.

A permission gets read as a description. B3 explicitly allows a combinational path from strobe to acknowledgement. A slave built that way does answer in the same cycle — and somebody who has only seen that slave has seen ACK assert immediately every time.

Classic has no stall signal. In an interface with an explicit backpressure wire, waiting is visible as a signal. Here, waiting is the absence of a signal, so a beginner reading a waveform sees "nothing happening" rather than "the slave is throttling".

All three are true observations. The compression drops the conditions.

2. What The Specification Says

Verified against the B3 source this run, with scope preserved.

Termination answers a request — it does not answer it at any particular time:

RULE 3.35 — ACK_O, ERR_O, RTY_O must be generated in response to the logical AND of CYC_I and STB_I.

RULE 3.50 — SLAVE ACK_O / ERR_O / RTY_O MUST be asserted and negated in response to the assertion and negation of STB_I.

In response to is a causal requirement, not a temporal one. Neither rule contains a cycle count.

And the timing sections say so directly. RULE 3.75 makes the §3.2.1 and §3.2.2 timing normative for interfaces supporting single reads and writes, and those sections state that the slave "may insert wait states before asserting ACK_I, thereby allowing it to throttle the cycle speed", and that "any number of wait states may be added."

Combinational termination is permitted, not required:

PERMISSION 3.30 — The assertion of ACK_O, ERR_O, and RTY_O MAY be asynchronous to the CLK_I signal — that is, there may be a combinatorial logic path between STB_I and ACK_O.

OBSERVATION 3.40 — The asynchronous assertion assures that the interface can accomplish one data transfer per clock cycle.

A PERMISSION grants an option. It does not describe every slave, and the observation tells you what the option buys rather than what conformance demands.

And the specification names the cost of taking it:

OBSERVATION 3.50 — In large high speed designs the asynchronous assertion could lead to unacceptable delay times, caused by the loopback delay from the MASTER to the SLAVE and back to the MASTER.

OBSERVATION 3.45 — … slave wait states are easiest implemented using a registered ACK_O.

One rule people cite in the wrong direction:

RULE 3.55 — MASTER interfaces MUST operate normally when the SLAVE holds ACK_I asserted.

PERMISSION 3.35 — Under certain circumstances SLAVE interfaces MAY be designed to hold ACK_O asserted.

RULE 3.55 constrains the master, and PERMISSION 3.35 carries an explicit scope qualifier. Neither says slaves generally hold ACK — and a master that reads a held level as several completions has a master bug the specification warned it about.

3. Four Legal Latencies, Measured

One master, one four-operation program, four slave configurations differing only in latency and whether the termination leaves a flip-flop. Word 15 increments on every committed write, so the side-effect count is observable rather than idempotent.

  slave                transfers  wait clocks  commits  completion cycles
  0 waits, comb                4            0        2  2 7 12 17
  1 wait,  comb                4            4        2  3 9 15 21
  3 waits, comb                4           12        2  5 13 21 29
  0 waits, registered          4            4        2  3 9 15 21

  ARCHITECTURAL RESULT
  increment register   1 / 1 / 1 / 1
  last value read      0x00000001 / 0x00000001 / 0x00000001 / 0x00000001
  protocol violations  0 / 0 / 0 / 0
  unknown pins         0 / 0 / 0 / 0

Four latencies. One architectural outcome. Zero protocol violations in every column.

If the claim were true, three of these four configurations would be illegal — and the conformance checker, which implements RULES 3.25, 3.30, 3.35, 3.45, 3.50 and 3.60, disagrees in all four.

4. The Registered Row

The fourth rig is configured for zero wait states and still waits four clocks across four transfers — landing exactly on the one-wait row, completion cycles and all.

Nothing is wrong. Its termination comes out of a flip-flop, so the master cannot observe the answer until the clock after the slave decided it. One extra clock per transfer, in this implementation.

What that measurement supports and does not:

Supported. For this slave, registering the termination cost one clock per transfer and left the committed data, the read-back value, the commit count and the protocol result unchanged.

Not supported. That registered slaves are slow; that combinational termination is faster in any system-level sense; any claim about frequency at all. The benefit of registering is on the other side of OBSERVATION 3.50 — breaking the loopback path — and measuring that needs synthesis, which this curriculum has not run.

Chapter 28.4 put the discipline as: say which half you measured. Here the latency half is measured and the frequency half is not.

5. What Actually Must Be True

The misconception attaches "must" to the wrong signal. Three things genuinely must hold while a phase is open, and none of them is a deadline:

And one thing must not be inferred: a deadline. B3 bounds no latency. If your system has one, it comes from a requirements document — the nearest the specification comes is RECOMMENDATION 3.10, suggesting a watchdog in an interconnect as one solution to deadlock, with no duration, no response and no recovery defined. Chapter 30.4 measured a nine-clock wait passing and an unbounded one cut off at twenty, and the number twenty came from nowhere but a choice.

6. The Design Consequence

A master that cannot wait. A master built on the assumption samples the termination in a fixed window and mis-completes, or hangs, against any slave that throttles. It will pass every test run against a zero-wait model.

A slave that must not wait. Forcing combinational termination onto a slave with real internal latency means either lying — terminating before the work is done — or accepting the loopback path OBSERVATION 3.50 describes, in a design where it may not close.

A test suite that only runs at zero latency. The most common and least visible. Chapter 30.1 measured two defects that are structurally unable to exist at zero waits: at zero latency the phase has no interior, so nothing can move inside it and nothing can happen twice. A suite that runs only there has not tested the design; it has avoided it.

7. The Replacement Statement

8. What To Carry Forward

• ACK is a termination, not a schedule. In response to is causal, not temporal.
• A PERMISSION describes an option somebody took, never every implementation.
• Four legal latencies produced one architectural result and zero violations.
• RULE 3.55 constrains the master, and PERMISSION 3.35 carries an explicit scope qualifier.
• Say which half you measured. One clock per transfer, measured; frequency, not.
• Test at more than one latency, or a whole defect class cannot exist in your test bench.

Chapter 31.6 closes the module, and the curriculum.