Wishbone · Module 31
"Wishbone Is Only for Hobby Projects"
Same RTL, same protocol, same zero protocol violations: one test reports nothing and the other reports six misrouted addresses.
This claim is harder to dismantle than the previous two, because "hobby" is not a technical property of an interface at all. There is no port, no timing parameter and no rule that differs.
So the useful work is not defending the protocol. It is separating five variables that the word silently merges.
1. Five Variables, One Word
| variable | what it actually describes | does the protocol determine it? |
|---|---|---|
| governance | who maintains it, under what process | no |
| deployment context | FPGA, ASIC, shuttle, simulation only | no |
| design quality | decode completeness, error handling, parameter checking | no |
| verification quality | sensitivity, independence, negative controls | no |
| protocol choice | which interface the ports speak | this one |
Only the last row is about Wishbone, and it is the row that carries none of the meaning people intend. A disciplined AXI peripheral and a careless AXI peripheral differ on rows three and four; so do two Wishbone peripherals. The bus name is constant across the entire quality range.
2. The Experiment That Settles It
Hold the protocol fixed. Vary the implementation, and vary the discipline of the test pointed at it. Four rigs, one interface.
First, what a casual bring-up test looks at — a scoreboard and the protocol checks:
WHAT A CASUAL TEST LOOKS AT - scoreboard and protocol only
implementation scoreboard protocol P0 protocol P2 verdict
weak 0 0 0 looks fine
disciplined 0 0 0 looks fineBoth pass. One of those implementations has an incomplete address decode and a byte-lane merge that ignores SEL.
Now the same two implementations under a test that seeds non-zero data, probes the window boundaries rather than the interior, and runs against a slave with wait states:
WHAT A DISCIPLINED TEST LOOKS AT - and it is the SAME RTL
implementation owner errors scoreboard delivered mask verdict
weak 6 2 f FAIL
disciplined 0 0 2 looks fine THE WEAK IMPLEMENTATION APPEARS IN BOTH TABLES.
The casual test reports 0 mismatches and 0 violations.
The disciplined test reports 6 misrouted addresses and 2
data mismatches, on identical RTL.Six addresses reaching a target the documented map does not assign them to, and a partial write delivered with mask f where 2 was asked for — with zero protocol violations in every column of both tables.
WHAT THE DISCIPLINED TEST DID DIFFERENTLY
seeded non-zero data before the partial write;
probed the window boundaries, not just the interior;
ran against a slave with wait states.Three decisions. None is about the protocol; all three are about the engineer.
3. Reading The Result Correctly
What this supports. For this implementation pair and these two stimuli, the defects were invisible to a scoreboard-and-protocol-checks test and visible to one that seeded data, swept boundaries and inserted wait states.
What this does not support. Anything about any project's quality, anyone's competence, or whether Wishbone designs are on average better or worse than designs using other interfaces. That last question would need a survey nobody has run, and this experiment is not it.
The transferable claim is narrower and stronger:
Protocol name does not confer engineering rigor. What a review can read is the decode, the error handling, the parameter checking, and whether the tests could have failed.
4. What Evidence About A Project Actually Supports
Module 29 inspected five repositories at recorded commits. The discipline there applies exactly here, and it is worth restating because this is the chapter where people reach for the wrong conclusion.
| finding | supports | does not support |
|---|---|---|
| a repository contains a Wishbone interface at commit X | that repository, at that commit | anything about other projects |
| its header states a B4 pipelined profile | the profile of that file | that Wishbone is pipelined |
| it carries formal properties in-file | those properties exist | that they were run, or pass |
| it is not a fork and not archived | its status on the check date | its status later |
| it is an Apache-2.0 harness with a Wishbone slave port | the contract that harness defines | how many chips, or that any worked |
None of those rows supports "industry standard", and none supports "hobby" either. Both labels are claims about a population, and five repositories are not a population.
5. What A Reviewer Can Actually Read
If the label is empty, what replaces it? The six chapters of Module 30, applied to the specific artifact in front of you:
| question | evidence | from |
|---|---|---|
| does the decode cover the documented map? | a boundary sweep, owner errors 0 | 30.3 |
| does an accepted write commit exactly once? | commit census against a non-idempotent target | 30.1 |
| could the tests have failed? | a negative control per detector | 30.2 |
| is the predictor independent of the design? | classified model inputs | 30.2 |
| does every termination reach its owner? | provenance, owner beside recipient | 30.4 |
| can it be debugged? | target, owner and commit observable on a port | 30.5 |
Six questions, all answerable from the artifact, none answerable from the protocol name. An unfamiliar block that answers all six is a good block regardless of which bus it speaks; one that answers none is not rescued by speaking a fashionable one.
6. The Design Consequence
Rejecting a block for its bus. A peripheral with a complete decode, tested at two latencies, with negative controls, is a lower integration risk than an untested one, whichever interface each of them speaks. The name is not the evidence, and treating it as the evidence means declining evidence you already have.
Accepting a block for its bus. The symmetric and more expensive error. The four rigs above are the demonstration: the weak implementation passes a casual test with zero violations on every column, and "it uses a serious protocol" adds exactly nothing to that result.
7. The Replacement Statement
| Instead of | "Wishbone is only for hobby projects." |
| Say | "Project category is not an interface property. What determines whether a block is safe to integrate is its decode coverage, error handling, parameter checking and the sensitivity of its tests — and those vary independently of the protocol. Ask the artifact the six review questions; the bus name answers none of them." |
8. What To Carry Forward
- Five variables, one word. Only one of them is the protocol, and it is the one that carries no meaning.
- The same RTL passed and failed depending on the test pointed at it — six misrouted addresses, zero protocol violations, identical design.
- A casual test that reports nothing has told you about the test.
- Evidence about a repository supports that repository at that commit. Not a population, in either direction.
- The six review questions are answerable from the artifact. Use them instead of the label.
Chapter 31.4 takes the word that makes protocol comparisons useless.
Continue learning
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"Wishbone Is Obsolete"
Eight different claims hide inside one word, each needing different evidence — and three design contexts that reach three different conclusions from the same protocol.
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Need for Standardized Interconnects
An address map answers where a register lives. It says nothing about which wires carry the request, when they are valid, how the target reports completion, or what happens on an error. Three peripherals with three private interfaces produce three adapters, three verification efforts and three ways to be wrong — which is the argument for standardising the interface rather than the map.
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The Open Hardware Movement
Source availability and reusability are different properties. A published core tells you what it does; it does not tell you what it requires, and requirements are what integration runs on. What reusable open IP needs beyond the RTL — licensing, documentation, an interface contract, verification, maintenance — and where open hardware is honestly weaker than its advocates claim.
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SoC Communication
Six chapters built the pieces; this one assembles them into a working fabric and traces three real accesses through it. The result works, and reading the nine unwritten rules a third party would need is what makes the case for a published protocol concrete rather than theoretical.
Standards & specifications
- Governing standard
- Wishbone SoC Interconnection Architecture (OpenCores)(opens OpenCores in a new tab)
Defines the Wishbone signal set, the bus cycles built from it and the interface rules a portable IP core must follow. It deliberately leaves interconnect topology, address map and arbitration policy to the integrator, so those are system decisions rather than requirements of the specification.
This page also covers RTL structure, verification approach and debugging technique. Those are engineering practice built on the standard, not requirements the standard itself imposes.
Where this fits
Part of the Wishbone curriculum.
