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UVM RAL Verification Labs
Lab 21of 25

  1. RAL Foundations and Register Modeling5

  2. Register Access and State Synchronization5

  3. Register Access Policies and Hardware Side Effects5

  4. Advanced Register Architecture and Verification5

  5. Expert RAL Debugging and Integrated IP Verification5

Lab 21Expert RAL Debugging and Integrated IP VerificationPublished

Wide Register Verification

Advanced~105 min

Problem statement

How do you verify a 64-bit register accessed through a 32-bit APB interface, including word ordering, partial writes, and prediction consistency?

Learning objective

Verify a 64-bit register over a 32-bit bus: word order, the effect of writing only one half, and a mirror that stays consistent across both bus transfers.

Prerequisite concepts

  • Address map byte width and endianness (Lab 03)
  • Explicit register prediction (Lab 09)

Concepts covered

  • 64-bit register
  • Word ordering
  • Endianness
  • Partial write
This lab is part of UVM RAL Verification Labs

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