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UVM RAL Verification Labs
Lab 9of 25

  1. RAL Foundations and Register Modeling5

  2. Register Access and State Synchronization5

  3. Register Access Policies and Hardware Side Effects5

  4. Advanced Register Architecture and Verification5

  5. Expert RAL Debugging and Integrated IP Verification5

Lab 09Register Access and State SynchronizationPublished

Explicit Register Prediction

Intermediate~90 min

Problem statement

How do you connect uvm_reg_predictor to an APB monitor and verify register mirror updates from observed bus transactions?

Learning objective

Disable auto-prediction, connect a uvm_reg_predictor to the APB monitor's analysis port, and show that the mirror tracks every observed transfer.

Prerequisite concepts

  • APB monitor and analysis ports
  • The APB register adapter (Lab 04)
  • Desired and mirrored values (Lab 06)

Concepts covered

  • uvm_reg_predictor
  • set_auto_predict(0)
  • bus_in
  • Explicit prediction
This lab is part of UVM RAL Verification Labs

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