Skip to content
VLSI Mentor
All UVM RAL labs
UVM RAL Verification Labs
Lab 4of 25

  1. RAL Foundations and Register Modeling5

  2. Register Access and State Synchronization5

  3. Register Access Policies and Hardware Side Effects5

  4. Advanced Register Architecture and Verification5

  5. Expert RAL Debugging and Integrated IP Verification5

Lab 04RAL Foundations and Register ModelingPublished

APB Register Adapter

Beginner~75 min

Problem statement

How do you implement an APB-to-RAL uvm_reg_adapter and translate register operations into actual bus transactions?

Learning objective

Implement reg2bus() and bus2reg() for APB so that every register operation becomes a correct APB transfer and every APB response returns a correct status and data.

Prerequisite concepts

  • APB transfer phases and PSLVERR
  • UVM sequence items
  • uvm_reg_bus_op fields

Concepts covered

  • uvm_reg_adapter
  • reg2bus()
  • bus2reg()
  • uvm_reg_bus_op
  • APB
This lab is part of UVM RAL Verification Labs

Unlock the complete lab with the UVM RAL Verification Labs collection.

Back to all labs