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UVM RAL Verification Labs
Lab 1of 25
RAL Foundations and Register Modeling5
Register Access and State Synchronization5
Register Access Policies and Hardware Side Effects5
Advanced Register Architecture and Verification5
Expert RAL Debugging and Integrated IP Verification5
Lab 01RAL Foundations and Register ModelingPublished
RTL Control Register and UVM Register Model
Beginner~60 min
Problem statement
How do you design a 32-bit RTL control register and create its corresponding uvm_reg model?
Learning objective
Write a 32-bit APB-accessible control register in RTL and a uvm_reg class whose size, fields and reset value describe exactly that hardware.
Prerequisite concepts
- SystemVerilog classes and parameterized types
- Synchronous register RTL with reset
- APB read and write transfers
Concepts covered
- uvm_reg
- configure()
- build()
- Reset value
This lab is part of UVM RAL Verification Labs
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