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UVM RAL Verification Labs
Lab 14of 25
RAL Foundations and Register Modeling5
Register Access and State Synchronization5
Register Access Policies and Hardware Side Effects5
Advanced Register Architecture and Verification5
Expert RAL Debugging and Integrated IP Verification5
Lab 14Register Access Policies and Hardware Side EffectsPublished
Hardware-Updated Status Registers
Intermediate~90 min
Problem statement
How do you verify a hardware-updated status register when the DUT changes register values independently of software writes?
Learning objective
Verify a status register that hardware updates on its own, mark the volatile fields correctly, and check them without false mirror mismatches.
Prerequisite concepts
- Read-clear and read-set fields (Lab 13)
- mirror() and its check mode (Lab 10)
Concepts covered
- Volatile fields
- Hardware update
- predict()
- Status register
This lab is part of UVM RAL Verification Labs
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