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UVM RAL Verification Labs
Lab 6of 25

  1. RAL Foundations and Register Modeling5

  2. Register Access and State Synchronization5

  3. Register Access Policies and Hardware Side Effects5

  4. Advanced Register Architecture and Verification5

  5. Expert RAL Debugging and Integrated IP Verification5

Lab 06Register Access and State SynchronizationPublished

Desired, Mirrored, and Actual Register Values

Intermediate~75 min

Problem statement

How do you use set(), get(), write(), read(), update(), and mirror() and demonstrate the differences between desired, mirrored, and actual DUT values?

Learning objective

Show, step by step, how each register API call changes the desired value, the mirrored value and the actual DUT value — and which calls generate bus traffic.

Prerequisite concepts

  • Frontdoor register access (Lab 05)
  • Register field modeling (Lab 02)

Concepts covered

  • Desired value
  • Mirrored value
  • set() / get()
  • update()
  • mirror()
This lab is part of UVM RAL Verification Labs

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